Configurable architecture for virtual socket client to an on-chip bus interface block
View Patent ↗An interface block provides an interface between an internal bus of an integrated circuit and a socket of a logic block. The interface block includes a synchronization module that performs any needed synchronization between a clock domain of the internal bus and a clock domain of the socket of the logic block. A translation module provides translation of block encoding of the data for data transferred between the internal bus and the socket of the logic block. A queue module buffers data flowing between the internal bus and the socket of the logic block. A driver module handles low level and electrical drive specifications of the internal bus.
1. An interface block that provides an interface between an internal bus and a socket of a logic block, the interface block, the internal bus and the logic block all being located within a single integrated circuit, the interface block comprising:
a synchronization module that performs any needed synchronization between a clock domain of the internal bus and a clock domain of the socket of the logic block;
a translation module that, for data transferred between the internal bus and the socket of the logic block, provides translation of block encoding of the data;
a queue module, that buffers data flowing between the internal bus and the socket of the logic block; and,
a driver module that handles low level and electrical drive specifications of the internal bus.
2. An interface block as in claim 1 wherein the synchronization module can be implemented as one of:
a null synchronization-block where no synchronization is required between the clock domain of the internal bus and the clock domain of the socket of the logic block;
a ratio synchronization block where the clock domain of the internal bus is related to the clock domain of the socket of the logic block by a fixed multiplier ratio; and,
a full synchronization block where there is no phase relationship between the clock domain of the internal bus and the clock domain of the socket of the logic block.
3. An interface block as in claim 1 additionally comprising a plurality of buffers used to pipeline the interface block, the plurality of buffers including:
a first buffer between the synchronization module and the translation module;
a second buffer between the translation module and the queue module; and,
a third buffer between the queue module and the driver module.
4. A method for providing an interface between an internal bus of an integrated circuit and a socket of a logic block within the integrated circuit, the method comprising the steps of:
(a) performing any needed synchronization between a clock domain of the internal bus and a clock domain of the socket of the logic block within a synchronization module;
(b) providing any required translation of block encoding of data transferred between the internal bus and the socket of the logic block using a translation module;
(c) buffering data flowing between the internal bus and the socket of the logic block using a queue module; and,
(d) handling low level and electrical drive specifications of the internal bus using a driver module.
5. A method as in claim 4 wherein step (a) comprises the following substeps:
(a.1) using a null synchronization block where no synchronization is required between the clock domain of the internal bus and the clock domain of the socket of the logic block;
(a.2) using a ratio synchronization block where the clock domain of the internal bus is related to the clock domain of the socket of the logic block by a fixed multiplier ratio; and,
(a.3) using a full synchronization block where there is no phase relationship between the clock domain of the internal bus and the clock domain of the socket of the logic block.
6. A method as in claim additionally comprising the following step:
(e) providing buffers between modules to allow pipelined operation.