High speed video frame buffer
View Patent ↗A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.
1. In a video data processing apparatus including a controller coupled to a memory circuit that has a plurality of arrays wherein adjoining ones of the plurality of arrays share clusters of sense amplifiers with each other, a method for storing video data in the memory circuit comprising the steps of:
segmenting a plurality of pixels representing one horizontal line of an image display panel into a plurality of pixel groups; and
storing data representing each of said plurality of pixel groups, respectively, in a row of a plurality of non-adjoining arrays in the memory circuit.
2. The method of claim 1 further comprising the steps of:
defining tiles of pixels by a two-dimensional grouping of the plurality of pixel groups from a plurality of horizontal lines of the display panel; and
storing data representing each tile of pixels substantially entirely in non-adjoining arrays in the memory circuit.
3. The method of claim 2 wherein the data representing each of said plurality of pixel groups is respectively stored in the same row of the plurality of non-adjoining arrays.
4. The method of claim 3 wherein the data representing each tile of pixels is respectively stored in consecutive rows of the plurality of non-adjoining arrays.
5. The method of claim 4 further comprising the steps of:
dividing the display panel into a first half and a second half;
storing pixel data from the first half of the panel in odd numbered arrays in the memory circuit; and
storing pixel data from the second half of the panel in even numbered arrays in the memory circuit.
6. In a video data processing apparatus including a controller coupled to a memory circuit that has a plurality of arrays wherein each odd numbered one of the plurality of arrays shares a cluster of sense amplifiers with an even numbered one of the plurality of arrays, a method for storing video data in the memory circuit comprising the steps of:
dividing the display panel into a first half and a second half;
storing pixel data from the first half of the panel in odd numbered arrays in the memory circuit; and
storing pixel data from the second half of the panel in even numbered arrays in the memory circuit.