Systems and methods for multi-tasking, resource sharing and execution of computer instructions
View Patent ↗In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.
1. A multi-tasking processor for executing computer instructions for a plurality of tasks, the processor being operable to either suspend a task or to re-execute a task's instruction without suspending the task, the processor comprising circuitry for:
scheduling tasks for execution, and executing tasks scheduled for execution;
obtaining first and second indications each of which is associated with a task being executed by the processor and with an instruction being executed for the associated task, each indication being an indication that the associated instruction is not to be executed to completion;
in response to each first indication, (i) suspending the associated instruction without executing the associated instruction to completion, and (ii) suspending the associated task, wherein suspended tasks are not scheduled for execution, the processor being operable to schedule another task for execution in lieu of the associated task; and
in response to each second indication, suspending the associated instruction without executing the associated instruction to completion and without suspending the associated task, and re-executing the associated instruction without suspending the associated task.
2. The processor of claim 1 wherein the circuitry is to schedule a task or tasks for execution on each instruction executed by the processor such that whenever the processor is to execute any instruction, the circuitry is to perform the task scheduling to schedule a task that will execute the instruction.
3. The processor of claim 1 wherein:
the processor comprises an instruction execution unit for executing instructions stored in a memory and fetched from the memory; and
on obtaining of any one of the first and second indications, the processor is operable to:
(a) suspend the associated instruction after the associated instruction has been fetched from the memory; and
(b) re-fetch the associated instruction from the memory to re-execute the associated instruction.
4. The processor of claim 1 wherein the associated instruction is suspended after being decoded by the processor, and the associated instruction is decoded again when the associated instruction is being re-executed by the processor.
5. The processor of claim 1 wherein suspension of the associated task and scheduling of another task in lieu of the associated task does not involve instruction execution by the processor.
6. The processor of claim 1 wherein the processor comprises an instruction execution pipeline operable to concurrently execute instructions from different tasks, wherein on obtaining of any one of the first and second indications the processor is operable to suspend the associated instruction after the pipeline starts execution of one or more other instructions for one or more tasks other than the associated task but before the pipeline starts execution of any instruction following the associated instruction for the associated task.
7. The processor of claim 6 wherein the pipeline comprises an instruction decode stage, and the associated instruction is suspended after being processed by the decode stage.
8. The processor of claim 6 wherein the associated instruction is suspended in the pipeline's read stage in which instruction operands are read from storage and presented to instruction execution logic.
9. The processor of claim 1 wherein at least one first indication is obtained when the associated instruction is accessing a first resource and the first resource is unavailable to the associated instruction, and at least one second indication is obtained when the associated instruction is accessing a second resource and the second resource is unavailable to the associated instruction.
10. The processor of claim 1 wherein at least one first indication is obtained when the associated instruction is to access an unavailable resource, and the associated task remains suspended until the resource becomes available.
11. The processor claim 10 wherein the processor executes the associated instruction to completion when the resource becomes available.
12. The processor of claim 10 wherein the resource is a FIFO shared by the associated task and at least one other task.
13. The processor of claim 10 wherein the resource is a FIFO.
14. The processor of claim 13 wherein the FIFO is a request FIFO for storing requests to process network data, and for at least one first indication the associated instruction is an instruction to read the request FIFO.
15. The processor of claim 13 wherein the FIFO is a command FIFO for storing commands for processing of network data, and for at least one first indication the associated instruction is an instruction to write one or more commands to the command FIFO.
16. The processor of claim 13 wherein the FIFO is a status FIFO for storing status information on reception of network data over a network, and for at least one first indication the associated instruction is an instruction to read the status FIFO.
17. The processor of claim 1 wherein for each first indication, the circuitry is operable to re-execute the associated instruction when the associated task becomes unsuspended and scheduled again for execution.
18. The processor of claim 1 wherein for each first indication, the circuitry is operable to execute the associated instruction to completion when the associated task becomes unsuspended and scheduled again for execution.
19. A method for executing computer instructions by a multi-tasking processor operable to either suspend a task or to re-execute a task's instruction without suspending the task, the method comprising:
scheduling tasks for execution, and executing tasks scheduled for execution;
obtaining first and second indications each of which is associated with a task being executed by the processor and with an instruction being executed for the associated task, each indication being an indication that the associated instruction is not to be executed to completion;
in response to each first indication, (i) suspending the associated instruction without executing the associated instruction to completion, and (ii) suspending the associated task, wherein suspended tasks are not scheduled for execution, the processor being operable to schedule another task for execution in lieu of the associated task; and
in response to each second indication, suspending the associated instruction without executing the associated instruction to completion and without suspending the associated task, and re-executing the associated instruction without suspending the associated task.
20. The method of claim 19 wherein scheduling a task or tasks for execution is performed on each instruction executed by any one of the tasks such that whenever an instruction is to be executed, the task scheduling is performed to schedule a task that will execute the instruction.
21. The method of claim 19 wherein each of the first and second indications is received after the associated instruction has been fetched from a memory for execution; and
the processor is operable to fetch the associated instruction again from the memory to re-execute the associated instruction.
22. The method of claim 19 wherein the first associated instruction is suspended after being decoded, and the associated instruction is decoded again when the associated instruction is being re-executed.
23. The method of claim 19 wherein suspension of the associated task and scheduling of another task in lieu of the associated task does not involve instruction execution.
24. The method of claim 19 wherein on obtaining of any one of the first and second indications the associated instruction is operable to be suspended while being executed in an instruction execution pipeline after the pipeline starts execution of one or more other instructions for one or more tasks other than the associated task but before the pipeline starts execution of any instruction following the associated instruction for the associated task.
25. The method of claim 24 wherein the pipeline comprises an instruction decode stage, and the associated instruction is suspended after being processed by the decode stage.
26. The method of claim 24 wherein the associated instruction is suspended in the pipeline's read stage in which instruction operands are read from storage and presented to instruction execution logic.
27. The method of claim 19 wherein at least one first indication is obtained when the associated instruction is accessing a first resource and the first resource is unavailable to the associated instruction, and at least one second indication is obtained when the associated instruction is accessing a second resource and the second resource is unavailable to the associated instruction.
28. The method of claim 27 wherein the first resource is a request FIFO for storing requests to process network data, and for at least one first indication the associated instruction is an instruction to read the request FIFO.
29. The method of claim 27 wherein the first resource is a command FIFO for storing commands for processing of network data, and for at least one first indication the associated instruction is an instruction to write one or more commands to the command FIFO.
30. The method of claim 27 wherein the first resource is a status FIFO for storing status information on reception of network data over a network, and for at least one first indication the associated instruction is an instruction to read the status FIFO.
31. The processor of claim 27 wherein when the associated task becomes suspended on obtaining the first indication, the associated instruction is canceled and the associated instruction is re-executed when the resource becomes available.
32. The method of claim 19 wherein at least one first indication is obtained when the associated instruction is to access an unavailable resource, and the associated task remains suspended until the resource becomes available.
33. The method of claim 32 wherein the associated instruction is re-executed when the resource becomes available.
34. The method of claim 32 wherein the resource is a FIFO shared by the associated task and at least one other task.
35. The method of claim 32 further comprising, on obtaining the first indication, executing the associated instruction to completion when the resource becomes available.
36. The method of claim 19 further comprising, for at least one first indication re-executing the associated instruction when the associated task becomes unsuspended and scheduled again for execution.
37. The method of claim 19 wherein for each first indication, the processor is operable to execute the associated instruction to completion when the associated task becomes unsuspended and scheduled again for execution.