Simple algorithmic cryptography engine
View Patent ↗A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs. A variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instructions that are expected to be commonly used in the programming of such processes. In a preferred low-cost embodiment, a single-port random-access memory (RAM) is used for operand storage, few data busses and registers are used in the data-path, and the instruction set is optimized for parallel operations within instructions. Because cryptographic processes are characterized by operations on wide data items, particular emphasis is placed on the efficient processing of multi-word operations, including the use of constants having the same width as an instruction word. A simplified arithmetic unit is provided that efficiently supports the functions typically required for cryptographic operations with minimal overhead. A microcode-mapped instruction set is utilized in a preferred embodiment to facilitate multiple parallel operations in each instruction cycle and to provide direct processing control with minimal overhead.
1. A processing system comprising:
a processor that is configured to execute program instructions,
a memory that is configured to contain operands, each operand having a corresponding operand address in the memory and
at least one address register that is configured to contain an operand address; and
wherein the processor is further configured to provide an address-zero flag that is asserted when the operand address is zero and wherein is configured to:
receive the operand address from the processor, and
provide the operand address as an addressing input to the memory only.
2. The processing system as claimed in claim 1 , wherein
the operand address lies within an operand-address-range, and
is sized to be a minimum size required to contain a span of the operand-address-range.
3. The processing system of claim 1 , wherein at least one instruction of the program instructions effects a modification of at least two address registers upon execution of the at least one instruction.
4. The processing system of claim 1 , wherein
the operand-address corresponds to a counting index, and
the at least one address register is further configured to decrement the operand address in response to a decrement command from the processor, thereby providing a counting operation based on the counting index.
5. The processing system as claimed in claim 1 , wherein:
the operand address lies within an operand-address-range having a lower-address and an upper-address, and
the program instructions include at least one of:
a circular-increment instruction that
increments the operand-address in the at least one address register, and
resets the operand-address in the at least one address register to correspond to the lower-address when the operand-address in the at least one address register is greater than the upper-address,
a circular-decrement instruction that
decrements the operand-address in the at least one address register, and
resets the operand-address in the at least one address register to correspond to the upper-address when the operand-address in the at least one address register is less than the lower-address,
thereby constraining the operand-address in the at least one address register to lie within the operand-address-range.
6. The processing system as claimed in claim 5 , further including at least one condition flag that is associated with at least one of:
the operand-address equaling the lower-address, and
the operand-address equaling the upper-address.