Microprocessor having a page prefetch cache for database applications
View Patent ↗A microprocessor cache configuration for reducing database cache misses and improving the processing speed, comprising a level-1 data cache, and a page prefetch cache. The page prefetch cache is adjacent the level-1 data cache. The page prefetch cache is configured to receive and store one or more database pages. Additionally, a page prefetch instruction provides the database pages to the page prefetch cache. The page prefetch instructions are generated by a compiler or by developer software.
1. A microprocessor cache, comprising:
a level-1 data cache;
a page prefetch cache adjacent said level-1 data cache, wherein when a database application is not employed, a validity bit disables the page pre-fetch cache, said page prefetch cache configured to receive and store one or more database pages; and
a means for generating a page prefetch instruction, said page prefetch cache configured to receive one of said database pages when a page prefetch instruction is executed, wherein the validity bit associated with said page prefetch cache is configured to one of enable and disable said page prefetch cache during database applications and said page prefetch cache is a fully associative buffer.
2. The microprocessor cache configuration of claim 1 , wherein said means for generating page prefetch instruction is a compiler.
3. The microprocessor cache configuration of claim 1 , wherein said means for generating prefetch instructions is provided by developer software.
4. The microprocessor cache configuration of claim 1 , wherein said page prefetch cache is configured on the same microprocessor as said level-1 data cache.
5. The microprocessor cache configuration of claim 1 , wherein said page prefetch cache is not configured on the same microprocessor as said level-1 data cache.
6. The microprocessor configuration of claim 4 , wherein said page prefetch cache is configured to receive and store a plurality of database pages.
7. The microprocessor configuration of claim 4 , wherein said page prefetch cache is configured to receive and store up to four database pages.
8. The microprocessor configuration of claim 1 , wherein said database pages have a page size ranging from 2 KB to 8 KB.
9. The microprocessor configuration of claim 1 , wherein said database pages have a page size up to 8 KB.
10. A microprocessor cache configuration for reducing database cache misses and improving the processing speed during database applications, comprising:
a level-1 data cache;
a page prefetch cache adjacent said level-1 data cache, wherein when a database application is not employed, a validity bit disables the page prefetch cache, said page prefetch cache configured to receive and store one or more database pages; and
a means for generating a page prefetch instruction, said page prefetch cache configured to receive one of said database pages when a page prefetch instruction is executed, wherein the validity bit associated with said page prefetch cache is configured to one of enable and disable said page prefetch cache during database applications and said page prefetch cache is a fully associative buffer.
11. The microprocessor cache configuration of claim 10 , wherein said means for generating page prefetch instruction is a compiler.
12. The microprocessor cache configuration of claim 10 , wherein said means for generating prefetch instructions is provided by developer software.
13. A microprocessor cache configuration, comprising:
a level-1 data cache; and
a page prefetch cache adjacent said level-1 data cache, wherein when a database application is not employed, a validity bit disables the page prefetch cache,
said page prefetch cache configured to receive and store one or more database pages when a page prefetch instruction is executed, wherein the validity bit associated with said page prefetch cache is configured to one of enable and disable said page prefetch cache during database applications and said page prefetch cache is a fully associative buffer.
14. A method for pre-fetching database pages, comprising:
enabling a page pre-fetch cache, wherein when a database application is not employed, a validity bit disables the page pre-fetch cache;
issuing a data pre-fetch cache request;
checking if at least one database page is in the page pre-fetch cache;
picking an entry in the page pre-fetch cache to replace;
making a page prefetch cache request;
submitting multiple requests to memory hierarchy; and
loading data returning from the multiple requests to the page prefetch cache, wherein the validity bit associated with said page prefetch cache is configured to one of enable and disable said page prefetch cache during database applications and said page prefetch cache is a fully associative buffer.