Methods for renaming stack references to processor registers

1. A method for renaming memory references to stack locations in a computer processing system comprising a plurality of processors, comprising the steps of:

fetching, by a first processor, an instruction referencing a stack;

replacing the instruction referencing the stack with a reference to a processor-internal register of the first processor and entering the reference to the processor-internal register in a dispatch table upon determining that the instruction uses an architecturally defined stack access method; and

performing a consistency-preserving operation to recover an in-order value for the instruction referencing the stack from a main memory, and entering the in-order value in the dispatch table upon determining that the stack reference references a register of a second processor.

2. The method according to claim 1 , wherein said step of performing the consistency-preserving operation comprises the step of bypassing a value from a given processor-internal register to a load operation that references a stack area and that does not use the architecturally defined stack access methods.

3. The method according to claim 1 , further comprising the step of synchronizing an architected state between the processor-internal registers and a main memory of the computer processing system, and wherein said step of performing the consistency-preserving operation recovers the in-order value for the stack reference from the main memory, upon performing said synchronizing step.

4. The method according to claim 3 , wherein the in-order value is written to the main memory by an in-order write operation inserted into an instruction stream containing an instruction corresponding to the instruction referencing the stack, when the instruction referencing the stack is a write stack reference.

5. The method according to claim 3 , further comprising the step of writing the in-order value to the main memory in response to a load operation that does not use the architecturally defined stack access methods.

6. The method according to claim 1 , wherein said step of performing a consistency-preserving operation comprises the steps of:

discarding all out-of-order state;

synchronizing an architected state between the processor-internal registers and the main memory of the computer processing system; and

restarting execution after a store operation has been performed that does not use the architecturally defined stack access methods.

7. The method according to claim 1 , wherein the architecturally defined stack access methods comprise memory accesses that use at least one of a stack pointer, a frame pointer, and an argument pointer.

8. The method according to claim 1 , wherein the architecturally defined stack access methods comprise push, pop, and other stack manipulation operations.

9. The method according to claim 1 , further comprising synchronizing an architected state between the processor-internal registers and a main memory of the computer processing system.

10. The program storage device according to claim 9 , wherein said synchronizing step comprises the step of inserting in-order write operations for all of the stack references that are write stack references.

11. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform methods steps for renaming memory references to stack locations in a computer processing system comprising a plurality of processors, the method steps comprising:

fetching, by a first processor, an instruction referencing a stack;

replacing the instruction referencing the stack with a reference to a processor-internal register of the first processor and entering the reference to the processor-internal register in a dispatch table upon determining that the instruction uses an architecturally defined stack access method; and

performing a consistency-preserving operation to recover an in-order value for the instruction referencing the stack from a main memory, and entering the in-order value in the dispatch table upon determining that the stack reference references a register of a second processor.

12. The program storage device according to claim 11 , wherein said step of performing a consistency-preserving operation comprises the step of bypassing a value from a given processor-internal register to a load operation that references a stack area and that does not use the architecturally defined stack access methods.

13. The program storage device according to claim 11 , further comprising the step of synchronizing an architected state between the processor-internal registers and a main memory of the computer processing system, and wherein said step of performing the consistency-preserving operation recovers the in-order value for the stack reference from the main memory, upon performing said synchronizing step.

14. The program storage device according to claim 13 , wherein the in-order value is written to the main memory by an in-order write operation inserted into an instruction stream containing an instruction corresponding to the instruction referencing the stack, when the instruction referencing the stack is a write stack reference.

15. The program storage device according to claim 13 , further comprising the step of writing the in-order value to the main memory in response to a load operation that does not use the architecturally defined stack access methods.

16. The program storage device according to claim 11 , wherein said step of performing a consistency-preserving operation comprises the steps of:

discarding all out-of-order state;

synchronizing an architected state between the processor-internal registers and the main memory of the computer processing system; and

restarting execution after a store operation has been performed that does not use the architecturally defined stack access methods.

17. The program storage device according to claim 11 , further comprising synchronizing an architected state between the processor-internal registers and a main memory of the computer processing system.

18. The program storage device according to claim 17 , wherein said synchronizing step comprises the step of inserting in-order write operations for all of the stack references that are write stack references.