System and method for validating processor performance and functionality
View Patent ↗A method and system for accurately validating performance and functionality of a processor in a timely manner is provided. First, a program is executed on a high level simulator of the processor. Next, a plurality of checkpoints are established. Then, state data at each of the checkpoints is saved. Finally, the program is run on a plurality of low level simulators of the processor in parallel, where each of the low level simulators is started at a corresponding checkpoint with corresponding state data associated with the corresponding checkpoint.
1. A computer-implemented method comprising the steps of:
executing a program on a high level simulator of a processor; thereafter
dividing the program into a plurality of independent code fragments such that a destination branch of an instruction in each code fragment falls within that code fragment; thereafter
establishing a plurality of checkpoints; wherein each of the plurality of checkpoints is established along a beginning point of a different one of the code fragments; thereafter
saving state data at each of said checkpoints; wherein said state data comprises:
program counter contents of said processor;
register contents of said processor;
cache memory contents of said processor;
main memory contents of processor; and
branch prediction contents of said processor; thereafter
executing instructions in said program on a plurality of low level simulators of said processor in parallel, starting each of said low level simulators at a corresponding checkpoint with corresponding state data associated with said corresponding checkpoint, wherein said executing instructions step further comprises the steps of:
loading each of said low level simulators with said program;
initializing each of said low level simulators at said corresponding checkpoint with said corresponding state data associated with said corresponding checkpoint; and
executing said program on said low level simulator up to a certain point in said program; and thereafter
generating functional data to validate functionality of the processor.
2. The computer-implemented method of claim 1 further comprising:
generating performance data to validate performance of the processor.
3. The computer-implemented method of claim 1 wherein each code fragments has one of random lengths and determined length.
4. The computer-implemented method of claim 1 wherein said processor is one of (a) a microprocessor, (b) a digital signal processor, (c) an input/output (I/O) controller, and (d) a network processor.
5. The computer-implemented method of claim 1 wherein said high level simulator is one of (a) an instruction accurate simulator (IAS) of said processor and (b) a cycle accurate simulator (CAS) of said processor.
6. The computer-implemented method of claim 1 wherein each of said low level simulators is a register transfer level (RTL) model of said processor, written as one of (a) a VHDL model of said processor and (b) a Verilog model of said processor.
7. The computer-implemented method of claim 1 wherein said certain point is one of (a) a next checkpoint immediately following said corresponding checkpoint, (b) a point in said program a random length after said corresponding checkpoint, and (c) a point in said program a determined length after said corresponding checkpoint.
8. A computer readable media having stored thereon a program comprising computer readable instructions for:
executing a program on a high level simulator of a processor; thereafter
dividing the program into a plurality of independent code fragments such that a destination branch of an instruction in each code fragment falls within that code fragment; thereafter
establishing a plurality of checkpoints; wherein each of the plurality of checkpoints is established along a beginning point of a different one of the code fragments; thereafter
saving state data at each of said checkpoints; wherein said state data comprises:
program counter contents of said processor;
register contents of said processor;
cache memory contents of said processor;
main memory contents of said processor; and
branch prediction contents of said processor; thereafter
executing instructions in said program on a plurality of low level simulators of said processor in parallel, starting each of said low level simulators at a corresponding checkpoint with corresponding state data associated with said corresponding checkpoint; wherein said executing of instructions further comprises the steps of:
loading each of said low level simulators with said program;
initializing each of said low level simulators at said corresponding checkpoint with said corresponding state data associated with said corresponding checkpoint; and
executing said program on said low level simulator up to a certain point in said program; and thereafter
generating functional data to validate functionality of the processor.
9. The computer readable media of claim 8 further comprising instructions for:
generating performance data to validate performance of the processor.
10. The computer readable media of claim 8 wherein each code fragment has one of random length and determined length.