Isochronous queue and buffer management
View Patent ↗A method of processing packets in a switch. A first queue is selected from at least three queues based on the cycle number (C) of a cycle and flushed at the start of cycle C. At least one isochronous packet is received over a bus during the cycle. The packet is placed in a second queue based on the cycle number.
1. A method of processing packets in a switch comprising:
selecting a first queue from at least three queues in a switch based on the cycle number (C) of a cycle;
flushing the first queue at the start of the cycle;
receiving at least one isochronous packet over a bus during the cycle;
placing the packet in a second queue based on the cycle number.
2. The method of claim 1 further comprising:
transmitting the packet from the second queue after two cycles.
3. The method of claim 1 wherein the first queue is chosen from four queues.
4. The method of claim 1 wherein the first queue is associated with a cycle that has a cycle number of C minus 1.
5. The method of claim 1 wherein the first queue number is the same as the second queue number.
6. The method of claim 1 wherein the first queue number is equal to the remainder of (C−1)/n wherein n is the number of queues in the switch.
7. The method of claim 1 wherein the second queue number is equal to the remainder of (C+2)/n wherein n is the number of queues in the switch.
8. The method of claim 1 further comprising:
transmitting packets in cycle C from a third queue wherein the queue number of the third queue is equal to the remainder of C/n wherein n is the number of queues in the switch.
9. The method of claim 1 further comprising:
setting a free pointer in the first queue to 0 at the end of the cycle; and
setting a used pointer in the first queue to 0.
10. The method of claim 1 further comprising:
setting a used pointer in the second queue to 0 at the end of the cycle; and
setting a free pointer in the second queue to n.
11. A switch in a network comprising:
a buffer memory including at least three egress queues; and
a processor to direct incoming isochronous packets into one of the egress queues based on a cycle number of the switch and to flush another of the egress queues based on the cycle number wherein the processor is configured to direct the incoming isochronous packets into the egress queue number equal to the remainder of (C+2)/n wherein n is the number of queues in the switch.
12. The switch of claim 11 wherein the switch is configured to be used with at least one bus.
13. The switch of claim 11 wherein the switch is configured to be used with a connection selected from the group: ethernet bus, asynchronous transfer mode bus, IEEE 1394 standard bus, T-1, T-3, and OC-X.
14. The switch of claim 11 further comprising:
at least one ingress port; and
at least one egress port
wherein each egress port is associated with at least three egress queues.
15. The switch of claim 14 wherein the egress queues store data to be transmitted by the processor from each egress port.
16. The switch of claim 11 wherein the buffer memory includes four queues.
17. A switch in a network comprising:
a buffer memory including at least three egress queues; and
a processor to direct incoming isochronous packets into one of the egress queues based on a cycle number of the switch and to flush another of the egress queues based on the cycle number wherein the processor is configured to flush the egress queue number equal to the remainder of (C−1)/n wherein n is the number of queues in the switch.
18. A switch in a network comprising;
a buffer memory including at least three egress queues; and
a processor to direct incoming isochronous packets into one of the egress queues based on a cycle number of the switch and to flush another of the egress queues based on the cycle number wherein the processor is configured to transmit the isochronous packets from the egress queue number equal to the remainder of C/n wherein n is the number of queues in the switch.