IP Library Granted Patent US 6,842,823
Granted Patent B1
US 6,842,823 · App. 09/550,108 · Granted Jan 11, 2005

Methods and apparatus for persistent volatile computer memory

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Quick Facts
Patent No.
US 6,842,823
App. No.
09/550,108
Granted
Jan 11, 2005
Kind
B1
Abstract

A method and apparatus for persistent volatile computer memory. In one embodiment, the memory of a computer in partitioned into two regions, one directly accessible to the operating system and one accessible to the operating system only through an intermediary program such as a device driver. In another embodiment, the partitioning of computer memory is achieved through modifications to the computer's BIOS, preventing the operating system from directly addressing a region of volatile computer memory and protecting the contents of the region from modification during a boot cycle.

Claims (53)

1. In a computer system comprising an operating system, an intermediary program, and a volatile memory, a method for providing a persistent region of the volatile memory, the method comprising the steps of:

(a) partitioning the volatile memory into a first, contiguous, non-persistent memory region and a second, contiguous, persistent memory region;

(b) providing an intermediary program in communication with the second, persistent memory region such that the second, persistent memory region is accessible to the operating system solely through the device driver.

2. The method of claim 1 wherein the contents of the second, persistent memory region are not initialized during a boot cycle.

3. The method of claim 1 wherein the second, persistent memory region comprises a look-aside buffer used by the intermediary program for atomic update and storage of write requests.

4. The method of claim 1 wherein step (a) comprises the steps of:

(a-a) reading a stored address defining the start address of the second, persistent memory region;

(a-b) reading a stored value defining the size of the second, persistent memory region; and

(a-c) creating a second, persistent memory region at the start address equal in size to the stored value defining the size of the second, persistent memory region.

5. The method of claim 4 wherein the program reads the stored addresses and stored values defining the size of the second, persistent memory region from a non-volatile memory element.

6. An operating system memory environment comprising:

a first, contiguous memory mode region of volatile memory accessible to users and to the operating system;

a second, contiguous memory mode region of volatile memory accessible only to the operating system and not to users; and

a third, contiguous memory mode region of volatile memory not accessible by users and not directly accessible by the operating system.

7. The operating system memory environment of claim 6 wherein the operating system is a Microsoft Windows operating system.

8. A computers operating under control of a memory-mapped operating system, the computer comprising:

a volatile memory including a first, contiguous non-persistent memory region that is mapped by the operating system; and

a second, contiguous, persistent memory region that is not mapped by the operating system.

9. The computer of claim 8 further comprising:

a device driver in communication with the operating system and the second, persistent region of volatile memory,

wherein the operating system addresses the second, persistent region of volatile memory using the device driver.

10. The computer of claim 9 wherein the second, persistent region of volatile memory comprises a look-aside buffer used by the device driver for atomic update and storage of write requests.

11. The computer of claim 8 wherein the locations of the second, persistent region of volatile memory are mapped by the operating system or a user application upon completion of the boot cycle.

12. A computer operating under control of an operating system, the computer comprising:

a volatile memory, including a first, contiguous, non-persistent memory region, the first non-persistent memory region directly accessible by the operating system, and initialized during a boot cycle, and a second contiguous persistent memory region not directly accessible by the operating system and not initialized during a boot cycle; and

an intermediary program in communication with the operating system and the second, persistent memory region;

wherein the intermediary program enables the operating system to address the second, persistent memory region.

13. The computer of claim 12 wherein the first, non-persistent memory region and the second, persistent memory region comprise different physical volatile memory elements.

14. The computer of claim 12 wherein the intermediary program is a device driver.

15. The computer of claim 12 additionally comprising:

a basic input/output system (BIOS) preventing direct access to the second, persistent memory region by the operating system.

16. The computer of claim 12 wherein the second, persistent memory region is allocated to redundant CPU memory locations.

17. The computer of claim 12 additionally comprising:

a non-volatile memory element storing information concerning the configuration of the second, persistent memory region.

18. The computer of claim 12 additionally comprising:

a non-volatile memory element storing information concerning the configuration of the first, non-persistent memory region.

19. The computer of claim 12 additionally comprising:

a file storing information concerning the configuration of the second, persistent memory region.

20. The computer of claim 12 additionally comprising:

a file storing information concerning the configuration of the first, non-persistent memory region.

21. The computer of claim 12 wherein the persistent memory region comprises:

a look-aside buffer, comprising:

a set of state bits, and

a buffer region for the storage of data, wherein the look-aside buffer is used for the atomic storage and update of write requests.

22. A storage medium having embodied thereon a program which, when loaded into a computer having an operating system and a volatile memory partitioned into a first, contiguous non-persistent memory region and a second, contiguous, persistent memory region, provides the computer with a persistent, volatile memory, said program comprising:

computer-readable program means for reading from the second, persistent memory region in response to requests coming from the operating system; and

computer-readable program means for writing to the second, persistent memory region in response to requests coming from the operating system.

23. The program of claim 22 wherein the second, persistent memory region of the computer comprises a look-aside buffer including a set of state bits and a buffer region for the storage of data, the program further comprising:

computer-readable program means for setting the state bits to a first value before writing the contents of a request to the buffer region;

computer-readable program means for writing the contents of a request to the buffer region;

computer-readable program means for setting the state bits to a second value after successful completion of the writing of the contents of a request to the buffer region;

computer-readable program means for copying the contents of the buffer region to the appropriate location in the second, persistent memory region; and

computer-readable program means for setting the state bits to a third value after successfully copying the contents of the buffer region to the appropriate location in the second, persistent memory region.

Assignments (6)
SECURITY INTEREST Recorded Apr 3, 2020
From: STRATUS TECHNOLOGIES IRELAND LIMITED
To: TRUST BANK (AS SUCCESSOR BY MERGER TO SUNTRUST BANK)
Reel/Frame 052316/0371 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2020
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: STRATUS TECHNOLOGIES IRELAND LTD.
Reel/Frame 052210/0411 →
RELEASE OF PATENT SECURITY AGREEMENT (SECOND LIEN) Recorded Apr 28, 2014
From: WILMINGTON TRUST NATIONAL ASSOCIATION; SUCCESSOR-IN-INTEREST TO WILMINGTON TRUST FSB AS SUCCESSOR-IN-INTEREST TO DEUTSCHE BANK TRUST COMPANY AMERICAS
To: STRATUS TECHNOLOGIES BERMUDA LTD.
Reel/Frame 032776/0536 →
RELEASE OF SUPER PRIORITY PATENT SECURITY AGREEMENT Recorded Apr 28, 2014
From: JEFFERIES FINANCE LLC
To: STRATUS TECHNOLOGIES BERMUDA LTD.
Reel/Frame 032776/0555 →
RELEASE OF INDENTURE PATENT SECURITY AGREEMENT Recorded Apr 28, 2014
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: STRATUS TECHNOLOGIES BERMUDA LTD.
Reel/Frame 032776/0579 →
SECURITY INTEREST Recorded Apr 28, 2014
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: SUNTRUST BANK
Reel/Frame 032776/0595 →