IGBT with amorphous silicon transparent collector
View Patent ↗The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.
1. A non punch-through IGBT device formed in a thin float zone wafer having a thickness of less than approximately 250 microns of silicon of one conductivity type; said wafer having a top surface and a bottom surface parallel to said top surface; a DMOS structure formed in said top surface of said wafer; a weak collector structure formed on said bottom surface of said wafer; said weak collector structure comprising a thin layer of amorphous silicon having a conductivity opposite to that of said thin float zone wafer; and a collector electrode formed atop said amorphous silicon layer.
2. The device of claim 1 , wherein said wafer has a thickness in the range of 80 microns to 250 microns.
3. The device of claim 1 , wherein said wafer is of the N conductivity type and said amorphous silicon is of the P conductivity type.
4. The device of claim 1 , wherein said collector electrode comprises aluminum.
5. The device of claim 3 , wherein said collector electrode comprises aluminum.
6. The device of claim 5 , wherein said collector electrode includes titanium, nickel vanadium and silver layers atop said aluminum.
7. The device of claim 1 , wherein said amorphous silicon layer is about 0.05 to about 0.5 microns thick.
8. A semiconductor device formed in a float zone wafer having a thickness of less than approximately 250 microns of silicon of one conductivity type; said wafer having a top surface and a bottom surface parallel to said top surface; a PN junction pattern diffused into said top surface and a top electrode connected to said top surface; a main electrode structure formed on said bottom surface of said wafer; said main electrode structure comprising a thin layer of amorphous silicon having a conductivity opposite that of said thin float zone wafer and a metallic electrode formed over said amorphous silicon layer.
9. The device of claim 8 , wherein said wafer has a thickness in the range of 100 microns to 250 microns.
10. The device of claim 8 , wherein said wafer is of the N conductivity type and said amorphous silicon is of the P conductivity type.
11. The device of claim 8 , wherein said metallic electrode comprises aluminum.
12. The device of claim 11 , wherein said metallic electrode further includes titanium, nickel, vanadium and silver layers atop said aluminum.
13. The device of claim 8 , wherein said amorphous silicon layer is about 0.05 to about 0.5 microns thick.