Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units
View Patent ↗A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
1. A method for determining an output of a finite impulse response digital filter having L filter coefficients in response to a set of M input samples, comprising the steps of:
(a) loading a first input sample into a first location in a first register;
(b) loading a second input sample into a second location in said first register while leaving a value of the first location in said first register unchanged;
(c) loading two aligned coefficients into a second register;
(d) computing two or more intermediate results using contents of the first and second registers,
(e) loading a new input sample into the first location in said first register while leaving a value of the second location in said first register unchanged;
(f) computing two or more intermediate results using contents of the first and second registers;
(g) repeating steps (b)–(f) for L iterations to provide two or more output samples;
(h) repeating steps (a)–(g) for M/2 iterations to provide M output samples; and
wherein each of step (a), (b) and (e) comprises an aligned memory access.
2. A method as defined in claim 1 wherein said input samples and said coefficients are 16 bits each.
3. A method as defined in claim 1 wherein steps (d) and (f) each comprise multiply accumulate operations.
4. A method as defined in claim 1 wherein steps (d) and (f) each comprise selecting operands from the first and second registers in response to computation instructions and performing multiply accumulate operations on the selected operands.
5. A method as defined in claim 1 wherein step (d) comprises a multiply accumulate operation on a first coefficient in said second register and the input sample in the first location in said first register, and a multiply accumulate operation on the first coefficient in said second register and the input sample in the second location in said first register.
6. A method as defined in claim 5 wherein step (f) comprises a multiply accumulate operation on a second coefficient in said second register and the new input sample in the first location in said first register, and a multiply accumulate operation on the second coefficient in said second register and the input sample in the second location in said first register.