System and method for implementing an SMBus/I2C interface on a network interface card
View Patent ↗A system and method for implementing an SMBus/I 2 C interface in a computer connectable to a network. The system includes a plurality of devices communicably coupled to an SMBus. The system operates at a first clock rate when the system is awake, and at a second clock rate less than the first clock rate when the system is sleeping. At least when the system is sleeping, a first device stores data transferred via the SMBus in a register, and a second device drives the clock line of the SMBus to a low logic level while the data is stored in the register of the first device. Upon completion of the data transfer operation, the first device clears the data from the register, and the second device releases the clock line to allow it to be pulled-up by pull-up circuitry connected to the SMBus.
1. A system for transferring data between a plurality of devices coupled to a bus, at least one of the plurality of devices being operative at a plurality of clock rates, comprising:
a bus including a data line operative to carry data and a clock line operative to carry a clock signal; and
first and second devices operatively coupled to the bus, at least the second device including at least one data register,
wherein the first and second devices are operative at a first clock rate, and the second device is further operative at a second reduced clock rate, the second reduced clock rate being less than the first clock rate,
wherein at least the first device is operative to transmit data over the data line, and
wherein the second device is operative to receive at least a portion of the data transmitted over the data line, to store the at least a portion of the data in the data register, and, in the event the first device is operating at the first clock rate and the second device is operating at the second reduced clock rate, to drive the clock line to a predetermined logic level while the data is stored in the data register, thereby enabling data transfer between the first device and the second device over the bus while the second device operates at the second reduced clock rate.
2. The system of claim 1 wherein the second device is further operative at least at the second reduced clock rate to clear the data from the data register upon completion of the data transfer.
3. The system of claim 1 wherein the second device further includes control circuitry for driving the clock line to the predetermined logic level and for releasing the clock line upon completion of the data transfer.
4. A method of transferring data between a plurality of devices coupled to a bus, at least one of the plurality of devices being operative at a plurality of clock rates, comprising the steps of:
providing a bus and first and second devices coupled to the bus, at least the second device including at least one data register, the first and second devices being operative at a first clock rate, the second device being further operative at a second reduced clock rate, the second reduced clock rate being less than the first clock rate, the bus including a data line for carrying data and a clock line for carrying a clock signal;
transmitting data over the data line by the first device;
receiving at least a portion of the data transmitted over the data line by the second device;
storing the at least a portion of the data transmitted over the data line in the data register by the second device; and
in the event the first device is operating at the first clock rate and the second device is operating at the second reduced clock rate, driving the clock line to a predetermined logic level while the data is stored in the data register by the second device, thereby enabling data transfer between the first device and the second device over the bus while the second device operates at the second reduced clock rate.
5. The method of claim 4 further including the step of clearing the data from the data register upon completion of the data transfer by the second device, the clearing step being performable by the second device operating at least at the second reduced clock rate.
6. The method of claim 4 wherein the driving step includes driving the clock line to the predetermined logic level by control circuitry included in the second device, and further including the step of releasing the clock line upon completion of the data transfer by the control circuitry within the second device.