Method of manufacturing spacers on sidewalls of titanium polycide gate
View Patent ↗Disclosed is a method for manufacturing a semiconductor device, more particularly to a method of forming a spacer on side-walls of a titanium polycide gate. The method for manufacturing the semiconductor device is as follows. There is provided a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed. Herein, the titanium polycide gate is fabricated by an etching step employing the patterned hard mask. Afterward, the substrate is thermal-treated at temperature of 700˜750° C. according to a gate re-oxidation process, thereby forming a re-oxidation layer on side-walls of the gate and on the substrate surface. Next, an oxide layer for spacer is deposited on the resultant at process temperature of 350˜750 C., and a nitride layer is deposited on the oxide layer. Thereafter, a spacer is formed on side-walls of the gate and the hard mask layer by blanket-etching the nitride layer, the oxide layer and the re-oxidation layer.
1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed, and wherein the titanium silicide layer, the polysilicon layer and the gate oxide layer are etched using the patterned hard mask as an etching mask to form a titanium polycide gate; re-oxidizing the substrate at temperature of 700˜750° C. to form a re-oxidation layer on a side wall of the gate and on a surface of the substrate;
depositing an oxide layer on the resultant structure at process temperature of 350˜750° C. to form a re-oxidation layer on a side wall of the gate and on a surface of the substrate;
depositing a nitride layer on the oxide layer; and
forming a spacer on the gate and on a side wall of the hard mask by blanket-etching the nitride layer, the oxide layer and the re-oxidation layer
wherein the oxide layer is formed by a low pressure chemical vapor deposition process (LPCVD) comprising a pyrolysis method of TEOS (Si(OC 2 H 5 )) at a temperature of 600˜710° C.
2. A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed, and wherein the titanium silicide layer, the polysilicon layer and the gate oxide layer are etched using the patterned hard mask as an etching mask to form a titanium polycide gate;
re-oxidizing the substrate at temperature of 700˜750° C. to form a re-oxidation layer on a side wall of the gate an d on a surface of the substrate;
depositing an oxide layer on the resultant structure at process temperature of 350˜750° C. to form a re-oxidation layer on a side wall of the gate and on a surface of the substrate;
depositing a nitride layer on th e oxide layer; and
forming a spacer on the g ate and on a side wall of the hard mask b y blanket-etching the nitride layer, the oxide layer and the re-oxidation layer,
wherein the oxide layer is formed by a plasma enhanced chemical vapor deposition process (PECVD) comprising TEOS (Si (OC 2 H 5 )), O 2 gas and an inert gas at temperature of 350˜400° C.
3. A method of manufacturing a semiconductor device comprising the steps of:
providing a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed, and wherein the titanium silicide layer, the polysilicon layer and the gate oxide layer are etched using the patterned hard mask as an etching mask to form a titanium polycide gate;
re-oxidizing the substrate at a temperature of 700˜750° C. to form a re-oxidation layer on a side-wall of the gate and on a surface of the substrate;
forming an oxide layer on the resultant structure using a low pressure chemical vapor deposition process (LPCVD) employing a pyrolysis method of TEOS (Si(OC 2 H 5 )) at a temperature of 600˜710° C.;
depositing a nitride layer on the oxide layer; and
forming a spacer on the gate and on a side-wall of the hard mask by blanket-etching the nitride layer, the oxide layer, and the re-oxidation layer.
4. A method of manufacturing a semiconductor device comprising the steps of:
providing a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed, and wherein the titanium silicide layer, the polysilicon layer and the gate oxide layer are etched using the patterned hard mask as an etching mask to form a titanium polycide gate;
re-oxidizing the substrate at a temperature of 700˜750° C. to form a re-oxidation layer on a side-wall of the gate and on a surface of the substrate;
forming an oxide layer on the resultant structure using a plasma enhanced chemical vapor deposition (PECVD) employing TEOS (Si(OC 2 H 5 )), O 2 gas, and an inert gas at a process temperature of 350˜400° C.;
depositing a nitride layer on the oxide layer; and
forming a spacer on the gate and on a side-wall of the hard mask by blanket-etching the nitride layer, the oxide layer, and the re-oxidation layer.