Display system having floating point rasterization and floating point framebuffering
View Patent ↗A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.
1. A computer system, comprising:
a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization circuit coupled to the processor that rasterizes the primitive according to a scan conversion process which operates using a floating point format; and
a frame buffer coupled to the rasterization circuit for storing a plurality of color values in the floating point format.
2. The computer system of claim 1 further comprising:
a texture circuit coupled to the rasterization circuit that applies a texture to the primitive, wherein the texture is specified by floating point values; and
a texture memory coupled to the texture circuit that stores a plurality of textures in floating point values.
3. The computer system of claim 1 , wherein the floating point format is comprised of sixteen bits.
4. The computer system of claim 3 , wherein the floating point format is comprised of an s1Oe5 format.
5. The computer system of claim 1 further comprising a lighting circuit coupled to the rasterization circuit for performing a lighting function, wherein the lighting function executes on floating point values.
6. The computer system of claim 1 further comprising a fog circuit coupled to the rasterization circuit for performing a fog function, wherein the fog function operates on floating point values.
7. The computer system of claim 1 further comprising an antialiasing circuit coupled to the rasterization circuit which performs an antialiasing algorithm according to floating point values.
8. The computer system of claim 1 further comprising a blender coupled to the rasterization circuit which blends floating point values.
9. The computer system of claim 1 further comprising logic coupled to the rasterization circuit which performs per-fragment operations on floating point values.
10. The computer system of claim 1 , wherein the processor, the rasterization circuit, and the frame buffer are on a single semiconductor chip.
11. The computer system of claim 10 , wherein the processor, the rasterization circuit, and the frame buffer reside on a same substrate of the single semiconductor chip.
12. The computer system of claim 1 further comprising:
a display screen coupled to the frame buffer for receiving the plurality of color values read out from the frame buffer in the floating point format and displaying an image according to the plurality of color values.
13. The computer system of claim 1 further comprising:
an electrical connector for forwarding floating point color values from the frame buffer to a display screen.
14. In a computer system, a method for operating on data stored in a frame buffer, comprised of:
a) scan converting the data in a floating point format to produce floating point scan converted data;
b) storing the floating point scan converted data in the frame buffer in the floating point format;
c) reading the floating point scan converted data from the frame buffer;
d) operating directly on the floating point scan converted data in the floating point format to produce color data in the floating point format; and
e) writing the floating point color data to the frame buffer in the floating point format.
15. The method of claim 14 , wherein the steps of writing, storing, and reading are further comprised of specifying the floating point format according to a specification, wherein the specification corresponds to a level of range and precision.
16. The method of claim 15 wherein the specification is comprised of 16 bits of data and the data are comprised of one sign bit, ten mantissa bits, and five exponent bits.
17. The method of claim 15 wherein the specification is comprised of 17 bits of data and the data are comprised of one sign bit, 11 mantissa bits, and five exponent bits.
18. The method of claim 15 wherein the specification is comprised of 16 bits of data and the data are comprised of ten mantissa bits and six exponent bits.
19. The method of claim 15 wherein the specification is comprised of 32 bits of data and the data are comprised of one sign bit, 23 mantissa bits, and eight exponent bits.
20. A computer system comprising:
a raster subsystem for performing a rasterization process, the rasterization process performed in a floating point format; and
a floating point frame buffer coupled to the raster subsystem for storing a plurality of floating point color values, wherein the floating point color values are read out from the frame buffer in the floating point format for display.
21. The computer system of claim 20 , wherein the floating point color values are written to the frame buffer.
22. The computer system of claim 20 , wherein the floating point color values are read from the frame buffer for graphics processing.
23. The computer system of claim 20 , wherein the floating point color values are written to, read from, and stored in the frame buffer using a specification of the floating point color values that corresponds to a level of range and precision.
24. The computer system of claim 23 , wherein the floating point color values are comprised of 16 bits of data and the data are comprised of one sign bit, ten mantissa bits, and five exponent bits.
25. The computer system of claim 23 , wherein the floating point color values are comprised of 17 bits of data and the data are comprised of one sign bit, 11 mantissa bits, and five exponent bits.
26. The computer system of claim 20 wherein the raster subsystem performs a scan conversion process in a floating point format.
27. A rendering pipeline, comprising:
a processor for performing geometric calculations on a plurality of vertices of a primitive;
a rasterization module coupled to the processor that rasterizes the primitive according to a scan conversion process which operates using a floating point format; and
a frame buffer coupled to the rasterization module for storing a plurality of color values in the floating point format.
28. The rendering pipeline of claim 27 , further comprising:
a texture module coupled to the rasterization module that applies a texture to the primitive, wherein the texture is specified by floating point values; and
a texture memory coupled to the texture module that stores a plurality of textures in floating point values.
29. The rendering pipeline of claim 27 , wherein the floating point format is comprised of sixteen bits.
30. The rendering pipeline of claim 29 , wherein the floating point format is comprised of an s1Oe5 format.
31. The rendering pipeline of claim 27 , further comprising a lighting module coupled to the rasterization module for performing a lighting function, wherein the lighting function executes on floating point values.
32. The rendering pipeline of claim 27 , further comprising a fog module coupled to the rasterization module for performing a fog function, wherein the fog function operates on floating point values.
33. The rendering pipeline of claim 27 , further comprising an antialiasing module coupled to the rasterization module which performs an antialiasing algorithm according to floating point values.
34. The rendering pipeline of claim 27 , further comprising a blender coupled to the rasterization module which blends floating point values.
35. The rendering pipeline of claim 27 , further comprising logic coupled to the rasterization module which performs per-fragment operations on floating point values.
36. The rendering pipeline of claim 27 , wherein the processor, the rasterization module, and the frame buffer are on a single semiconductor chip.
37. The rendering pipeline of claim 36 , wherein the processor, the rasterization module, and the frame buffer reside on a same substrate of the single semiconductor chip.
38. The rendering pipeline of claim 27 further comprising:
a display screen coupled to the frame buffer for receiving the plurality of color values read out from the frame buffer in the floating point format and displaying an image according to the plurality of color values.
39. The rendering pipeline of claim 27 further comprising:
an electrical connector for forwarding floating point color values from the frame buffer to a display screen.