Semiconductor device having wiring patterns and dummy patterns covered with insulating layer
View Patent ↗A semiconductor device including a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area, circuit patterns formed on the substrate in the circuit area, a first dummy pattern which is formed of the same material as the circuit pattern, formed in the dummy area, the dummy pattern encompassing the circuit area, a first insulating layer formed on an entire surface of the semiconductor substrate, a second insulating layer formed only on the first insulating layer which is formed on the semiconductor substrate and on the circuit patterns; and a third insulating layer formed on the exposed first insulating layer and the second insulating layer.
1. A semiconductor device, comprising:
a semiconductor substrate having a first area where an integrated circuit is formed, a second area having a first part and a second part, and a third area where a pad pattern is formed, wherein the second area encompasses the first and third area;
wiring patterns formed on the substrate in the first area;
a first dummy pattern which is formed of the same material as the wiring patterns, formed in the first part of the second area, wherein the first part is located along an edge of the semiconductor substrate;
a second dummy pattern, which is formed of the same material as the wiring patterns, which is formed in the second part of the second area, wherein a second part is located between the first and the third areas, the first and the second dummy patterns being formed as a single integral structure, whereby the pad pattern is encompassed by the first and second dummy patterns;
a second insulating layer formed over the wiring patterns and the first and second dummy patterns, an edge of the second insulating layer being located on the pad pattern, which is adjacent the first and second dummy patterns; and
a first insulating layer formed above the semiconductor substrate, the first insulating layer being formed outside the first and second dummy patterns but not being formed over the first and second dummy patterns.
2. A semiconductor device as claimed in claim 1 , wherein the first insulating layer has a moisture absorbable characteristic.
3. A semiconductor device as claimed in claim 1 , wherein the first insulating layer is an SOG layer.
4. A semiconductor device as claimed in claim 1 , wherein the first dummy pattern has a width, which is fixed by a concentration of solid content of the first insulating layer.
5. A semiconductor device as claimed in claim 1 , further comprising a third insulating layer formed on the substrate, the first insulating layer being located between the second insulating layer and the third insulating layer.
6. A semiconductor device as claimed in claim 1 , wherein the width of the first dummy pattern is approximately 1 μm.
7. A semiconductor device as claimed in claim 1 , wherein the width of the second dummy pattern is approximately 1 μm.
8. A semiconductor device as claimed in claim 6 , wherein the width of the second dummy pattern is approximately 1 μm.
9. A semiconductor device as claimed in claim 1 , wherein the distance from the edge of the semiconductor substrate to the edge of the first dummy pattern is over 10 μm.
10. A semiconductor device as claimed in claim 6 , wherein the distance from the edge of the semiconductor substrate to the edge of the first dummy pattern is over 10 μm.
11. A semiconductor device as claimed in claim 7 , wherein the distance from the edge of the semiconductor substrate to the edge of the first dummy pattern is over 10 μm.
12. A semiconductor device as claimed in claim 8 , wherein the distance from the edge of the semiconductor substrate to the edge of the first dummy pattern is over 10 μm.