According to one embodiment a network switch is disclosed. The switch includes a first media access controller (MAC) coupled to a plurality of ports and a memory controller coupled to the first MAC. The memory controller is adaptable to write a first portion of packet data received from a first of the plurality of ports to a first memory device and write a second portion of the packet data from the first port to a second memory device.
1. A system comprising:
a memory, wherein the memory includes a plurality of logical memory devices; and
a network switch coupled to the memory, the network switch including a memory controller, wherein the switch is configured to sequentially write a first portion of received packet data to a first of the plurality of logical memory devices and to write a second portion of the packet data to a second of the plurality of logical memory devices and to write a third portion of the packet data to a third of the plurality of logical memory devices and
wherein the memory controller maintains a record identifying which of the plurality of logical memory devices was last written to; and
wherein the first of the plurality of logical memory devices comprises a synchronous static random access memories (SSRAMs) and the second and third of the plurality of logical memory devices comprise synchronous dynamic random access memories (SDRAMs).
2. The system of claim 1 wherein the memory controller comprises:
a first memory controller component coupled to the first logical memory device; and
a second memory controller component coupled to the second logical memory device.
3. The system of claim 2 wherein the first memory controller component and the second memory controller component access the corresponding logical memory devices via a shared address line.
4. The system of claim 1 wherein the network switch further comprises:
a receiver coupled to the memory controller;
a transmitter coupled to the memory controller;
address resolution logic coupled to the memory controller; and
packet queuing control coupled to the memory controller, the receiver, the transmitter and the address resolution logic.
5. The system of claim 4 wherein the network switch further comprises a media access controller (MAC) coupled to the receiver, wherein the MAC receives packet data via a plurality of ports coupled to the receiver.
6. The system of claim 4 wherein the memory controller comprises:
a first memory controller component coupled to the first logical memory device; and
a second memory controller component coupled to the second logical memory device.
7. A method comprising:
receiving a first data packet at a network switch;
performing a first memory write access wherein
a first portion of the first data packet is written to a first logical memory device coupled to the network switch
a second portion of the first data packet is written to a second logical memory device coupled to the network switch
a third portion of the first data packet is written to a third logical memory device coupled to the network switch, the third logical memory device having two banks;
determining at the network switch the logical memory device to which a portion of the first data packet was last written;
determining whether the size of a third portion of the data packet is less than a predetermined value; and
if so, writing the third portion of the data packet to both banks of the third logical memory device.
8. The method of claim 7 further comprising:
receiving a second data packet at the network switch;
writing a first portion of the second data packet to the first logical memory device; and
writing a second portion of the second data packet to the second logical memory device.
9. The method of claim 7 further comprising:
determining whether the size of the third portion of the data packet is less than a predetermined value; and
if not, writing a first sub-portion of the third portion of the data packet to a first bank of a third logical memory device and writing a second sub-portion of the third portion of the data packet to a second bank of the third logical memory device.
10. The method of claim 7 wherein the first, second and third logical memory devices comprise synchronous dynamic random access memories (SDRAMs).
11. The method of claim 7 wherein the first logical memory devices comprises a synchronous static random access memories (SSRAMs) and the second and third logical memory devices comprise synchronous dynamic random access memories (SDRAMs).
12. A method of switching packets within a network comprising:
receiving a first data packet from a first port;
parsing the first data packet into a plurality of first data packet portions;
writing a first data packet portion of the plurality of first data packet portions to a first logical memory device of a plurality of logical memory devices;
writing a second data packet portion of the plurality of first data packet portions to a second logical memory device of the plurality of logical memory devices;
receiving a second data packet from the first port;
parsing the second data packet into a plurality of second data packet portions;
determining which of the plurality of logical memory devices was the last of the plurality of memory devices to which one of the plurality of first data packet portions was written;
writing a first data packet portion of the plurality of second data portions to the first logical memory device if the first logical memory device is other than the last of the plurality of memory devices;
writing a second data packet portion of the plurality of second data portions to a fourth logical memory device if the fourth logical memory device is other than the last of the plurality of memory devices; and
writing a third data packet portion of the plurality of second data portions to a third logical memory device if the third logical memory device is other than the last of the plurality of memory devices.
13. A method comprising:
receiving a first data packet at a network switch; and
performing a first memory write access wherein
a first portion of the first data packet is written to a first logical memory device coupled to the network switch
a second portion of the first data packet is written to a second logical memory device coupled to the network switch and
a third portion of the first data packet is written to a third logical memory device coupled to the network switch;
determining whether the size of a third portion of the data packet is less than a predetermined value; and if so, writing the third portion of the data packet to both banks of the third logical memory device.
14. The method of claim 13 further comprising:
receiving a second data packet at the network switch;
writing a first portion of the second data packet to the first logical memory device; and
writing a second portion of the second data packet to the second logical memory device.
15. The method of claim 14 wherein, if the size of the third portion of the data packet is not less than a predetermined value, then writing a first sub-portion of the third portion of the data packet to a first bank of a third logical memory device and writing a second sub-portion of the third portion of the data packet to a second bank of the third logical memory device.
16. The method of claim 13 wherein, if the size of the third portion of the data packet is not less than a predetermined value, then writing a first sub-portion of the third portion of the data packet to a first bank of a third logical memory device and writing a second sub-portion of the third portion of the data packet to a second bank of the third logical memory device.
17. The method of claim 13 wherein the first, second and third logical memory devices comprise synchronous dynamic random access memories (SDRAMs).
18. The system of claim 17 wherein the first memory controller component and the second memory controller component access the corresponding logical memory devices via a shared address line.
19. The method of claim 13 wherein the first logical memory devices comprises a synchronous static random access memories (SSRAMs) and the second and third logical memory devices comprise synchronous dynamic random access memories (SDRAMs).