Memory sharing arrangement for an integrated multiprocessor system
View Patent ↗A multiprocessor system, more particularly for terminal devices of mobile radiotelephony, in which system are arranged on a common chip: at least two processors, at least one rewritable memory which can be accessed by the two processors, at least one cache memory via which the first processor has access to the memory, at least one bridge via which the second processor has access to the memory.
1. An electronic product, comprising:
a first processor coupled to an instruction cache and to a data cache;
a first bus coupled to the instruction cache and to the data cache;
a first memory coupled to the first bus;
a second processor coupled to a second bus;
a first bus bridge coupled to the first bus and to the second bus, the first bus bridge providing a path for transferring data between the first memory and the second processor;
a second memory coupled to the first bus;
a second bus bridge coupled to the second bus and a third bus, the third bus providing a data pathway within the first processor, the second bus bridge providing a path for transferring data between the second memory and the third bus of the first processor; and
a direct memory access (DMA) controller coupled to the second bus, the DMA controller configured to manage a transfer of data between the second memory and the second bus bridge;
wherein the first processor is configured to operate at a first frequency, the second processor is configured to operate at a second frequency, and the first frequency is greater than the second frequency, and wherein the first bus and the second bus are dissimilar.
2. The electronic product of claim 1 , wherein the first processor and the second processor are both disposed together on a single integrated circuit.
3. The electronic product of claim 2 , wherein the first processor is a digital signal processor, and the second processor is a microcontroller.
4. The electronic product of claim 3 , wherein a first portion of the first memory is dedicated to the first processor, a second portion of the first memory is dedicated to the second processor, and a third portion of the first memory is shared by the first and the second processors.
5. The electronic product of claim 4 , wherein the first bus has a first width, the second bus has a second width, and the third bus has a third width; the first width is greater than the second width, and the second width is greater than the third width.
6. The electronic product of claim 5 , wherein the DMA controller and the second bus are both disposed on the single integrated circuit.
7. The electronic product of claim 6 , wherein the first bus has a width of 128 bits, the second bus has a width of 32 bits, and the third bus has a width of 16 bits.
8. The electronic product of claim 6 , further comprising a Read Only Memory (ROM) disposed on the single integrated circuit and coupled to the second bus.
9. A mobile radiotelephony controller, comprising:
a digital signal processor coupled to an instruction cache and to a data cache;
a first bus coupled to the instruction cache and to the data cache;
a first memory coupled to the first bus;
a microcontroller coupled to a second bus;
a first bus bridge coupled to the first bus and to the second bus, the first bus bridge providing a path for transferring data between the first memory and the microcontroller;
a second memory coupled to the first bus;
a second bus bridge coupled to the second bus and a third bus, the third bus providing a data pathway within the digital signal processor, the second bus bridge providing a path for transferring data between the second memory and the third bus of the digital signal processor; and
a direct memory access (DMA) controller coupled to the second bus, the DMA controller configured to manage a transfer of data between the second memory and the second bus bridge;
wherein the digital signal processor is configured to operate at a first frequency, the microcontroller is configured to operate at a second frequency, and the first frequency is greater than the second frequency, wherein the first bus and the second bus are dissimilar, and wherein a first portion of the first memory is dedicated to the digital signal processor, a second portion of the first memory is dedicated to the microcontroller, and a third portion of the first memory is shared by the digital signal processor and the microcontroller.
10. The mobile radiotelephony controller of claim 9 , further comprising a ROM coupled to the second bus.
11. The mobile radiotelephony controller of claim 10 , wherein the first bus has a first width, the second bus has a second width, and the third bus has a third width; the first width is greater than the second width, and the second width is greater than the third width.
12. The mobile radiotelephony controller of claim 11 , wherein the digital signal processor, the microcontroller, the DMA controller, the ROM, the first memory, and the second memory are all disposed on the same single integrated circuit.