N-way demultiplexer
View Patent ↗In the preferred embodiment of the invention, an output clock synchronizes an output CPU with an n-way demultiplexer to allow the demultiplexer to know which output is which. To do so, the invention provides a synchronization scheme in which a synchronization string is always written to channel zero before the output is allowed to be clocked. Once synchronization is established, each channel has its own word-length output buffer. Thus, each time the clock sends out a signal, a new word is put into the output buffer, unless it happens to be for channel zero which does not need a memory.
1. A method for distributing high data rate output data to a number of different ports, comprising the steps of:
providing an output module having a plurality of different output channels;
providing a demultiplexer in communication with said output module for receiving said output channels;
providing an output dock for synchronizing said output module with said demultiplexer; and
providing a synchronization scheme in which a synchronization string is always written to a particular channel before said output channels are allowed to be clocked.
2. The method of claim 1 , further comprising the step of:
bonding together any predetermined number of channels for each of said ports independently of each of said other ports.
3. The method of claim 1 , further comprising the step of:
providing each output channel with its own output buffer;
wherein, once synchronization is established, each time said clock sends out a signal, a new word is put into an appropriate output buffer.
4. The method of claim 3 , further comprising the step of:
providing an address counter for controlling each said output buffer;
wherein said address counter waits for said synchronization string before counting through each of said output buffers.
5. The method of claim 4 , further comprising the step of:
providing a shift register associated with each said output buffer for receiving data in parallel as an input and for outputting said data in a serial fashion to an associated output buffer.
6. The method of claim 5 , further comprising the steps of:
connecting said shift registers together, such that by the time a first word is output from a first output buffer a next word may begin being output from said first output buffer; and
running a clock on said first output buffer and said next output buffer at a multiple of a rate that said clock would normally run for just said first output buffer.
7. An apparatus for distributing high data rate output data to a number of different ports in a system having an output module having a plurality of different output channels, said apparatus comprising:
a demultiplexer in communication with said output module for receiving said output channels;
an output clock for synchronizing said output module with said demultiplexer; and
a synchronization scheme in which a synchronization string is always written to a particular channel before said output channels are allowed to be clocked.
8. The apparatus of claim 7 , further comprising:
means for bonding together any predetermined number of channels for each of said ports independently of each of said other ports.
9. The apparatus of claim 7 , further comprising:
an output buffer each output channel;
wherein, once synchronization is established, each time said clock sends out a signal, a new word is put into an appropriate output buffer.
10. The apparatus of claim 9 , further comprising:
an address counter for controlling each said output buffer;
wherein said address counter waits for said synchronization string before counting through each of said output buffers.
11. The apparatus of claim 10 , further comprising:
a shift register associated with each said output buffer for receiving data in parallel as an input and for outputting said data in a serial fashion to an associated output buffer.
12. The apparatus of claim 11 , wherein said shift registers are connected together, such that by the time a first word is output from a first output a next word may begin being output from said first output; and further comprising:
a dock for clocking said first output and said next output, said clock running at a multiple of a rate that said clock would normally run for just said first output.