IP Library Granted Patent US 7,301,954
Granted Patent B1
US 7,301,954 · App. 09/668,407 · Granted Nov 27, 2007

Multiple-buffer queueing of data packets with high throughput rate

Assignee: United States of America as represented by the Secretary of the Navy
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Quick Facts
Patent No.
US 7,301,954
App. No.
09/668,407
Granted
Nov 27, 2007
Kind
B1
Abstract

The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data is organized into at least one chunk based on a linked list. The connection identifier identifies a connection in the channel. The data is part of a data stream associated with the connection. A packet memory of a second type provides access to the stored data when a transfer condition occurs.

Claims (89)

1. An apparatus comprising:

a first buffer memory of a first type to store data associated with a connection identifier corresponding to a channel in a network, the data being organized into at least one chunk based on a linked list, the at least one chunk comprising at least one chunk data block, the connection identifier identifying a connection in the channel, the data being part of a data stream of a packet associated with the connection, the packet having a defined packet size;

a packet memory of a second type coupled to the first buffer memory and configured to store the at least one chunk data block;

a second buffer memory of the first type coupled to the first buffer memory and the packet memory, and configured to store the at least one chunk data block; and

a write circuit (i) to write the at least one chunk data block to the packet memory in response to a transfer condition if the packet size indicates the packet is long, and (ii) to write the at least one chunk data block to the second buffer memory in response to the transfer condition if the packet size indicates the packet is short.

2. The apparatus of claim 1 further comprising:

a descriptor memory to store descriptor information corresponding to the at least one chunk; and

a controller coupled to the descriptor memory and the first buffer memory to control data transfer between the first buffer memory and the packet memory using the descriptor information.

3. The apparatus of claim 2 wherein the at least one chunk further comprises:

a chunk header to store chunk information associated with the linked list.

4. The apparatus of claim 3 wherein the chunk information includes at least one of a pointer to point to one other chunk, a size specifier to specify size of the at least one chunk, and a type specifier to specify type of the at least one chunk.

5. The apparatus of claim 4 wherein the at least one chunk is one of a head chunk corresponding to one end of the data stream, a linking chunk corresponding to an intermediate portion of the data stream, and a tail chunk corresponding to one other end of the data stream.

6. The apparatus of claim 5 wherein the descriptor information includes at least one of head and tail pointers, the head and tail pointers pointing to the head and tail chunks, respectively.

7. The apparatus of claim 6 wherein the connection identifier points to one of the head and tail pointers.

8. The apparatus of claim 2 wherein the controller comprises:

an ingress queue to buffer the data stream of the packet from an ingress of the channel; and

a queue segmenter to chunk the data stream into the at least one chunk.

9. The apparatus of claim 8 wherein the first buffer memory comprises an input buffer memory to store the at least one chunk transferred from the queue segmenter.

10. The apparatus of claim 9 wherein the input buffer memory comprises a queue associated with the connection identifier, the queue having a threshold and being configured to store the at least one chunk.

11. The apparatus of claim 10 wherein the transfer condition includes at least one of an overflow of the threshold, the packet size, and a scheduled egress request.

12. The apparatus of claim 11 wherein the controller further comprises:

a data combiner to combine the chunk data block of one chunk with the chunk data block of at least one other chunk in the input buffer memory;

wherein the write circuit (i) writes the combined chunk data block to the packet memory if the packet size indicates the packet is long, the combined chunk data block forming a contiguous data block in the packet memory, and (ii) writes the combined chunk data block to the second buffer memory if the packet size indicates the packet is short.

13. The apparatus of claim 12 wherein the controller further comprises:

a list creator to create an ordered list of pointers associated with chunk headers of the one and the at least one other chunk, the ordered list of pointers being transferred to the second buffer memory of the first type at a location pointed to by a head pointer;

a read circuit to burst transfer the contiguous data block from the packet memory to the second buffer memory using the ordered list of pointers in the second buffer memory if the packet size indicates the packet is long; and

an egress queue to buffer the contiguous data block transferred from the second buffer memory.

14. The apparatus of claim 13 wherein the first type is a static random access memory and the second type is a synchronous dynamic random access memory.

15. The apparatus of claim 14 wherein the input buffer memory and the second buffer memory have same sizes.

16. The apparatus of claim 14 wherein the input buffer memory and the second buffer memory have different sizes.

17. A method comprising:

storing data associated with a connection identifier corresponding to a channel in a network in a first buffer memory of a first type, the data being organized into at least one chunk based on a linked list, the at least one chunk comprising at least one chunk data block the connection identifier identifying a connection in the channel, the data being part of a data stream of a packet associated with the connection, the packet having a defined packet size; and

writing the at least one chunk data block (i) to a packet memory of a second type in response to a transfer condition if the packet size indicates the packet is long and (ii) to a second buffer memory of the first type in response to a transfer condition if the packet size indicates the packet is short.

18. The method of claim 17 further comprises:

storing descriptor information corresponding to the at least one chunk in a descriptor memory; and

controlling data transfer between the first buffer memory and the packet memory using the descriptor information.

19. The method of claim 18 wherein storing the data comprises:

storing chunk information associated with the linked list in a chunk header.

20. The method of claim 19 wherein the chunk information includes at least one of a pointer to point to one other chunk, a size specifier to specify size of the at least one chunk, and a type specifier to specify type of the at least one chunk.

21. The method of claim 20 wherein the at least one chunk is one of a head chunk corresponding to one end of the data stream, a linking chunk corresponding to an intermediate portion of the data stream, and a tail chunk corresponding to one other end of the data stream.

22. The method of claim 21 wherein the descriptor information includes at least one of head and tail pointers, the head and tail pointers pointing to the head and tail chunks, respectively.

23. The method of claim 22 wherein the connection identifier points to one of the head and tail pointers.

24. The method of claim 18 wherein controlling the data transfer comprises:

buffering the data stream of the packet from an ingress of the channel by an ingress queue; and

segmenting the data stream into the at least one chunk.

25. The method of claim 24 wherein storing the data comprises storing the at least one chunk transferred from the queue segmenter in an input buffer memory.

26. The method of claim 25 wherein storing the at least one chunk in the input buffer memory comprises storing the at least one chunk in a queue associated with the connection identifier, the queue having a threshold.

27. The method of claim 26 wherein the transfer condition includes at least one of an overflow of the threshold, the packet size, and a scheduled egress request.

28. The method of claim 27 wherein controlling the data transfer further comprises:

combining the chunk data block of one chunk with the chunk data block of at least one other chunk in the input buffer memory.

29. The method of claim 28 wherein controlling the data transfer further comprises:

creating an ordered list of pointers associated with the chunk headers of the one and the at least one other chunk, the ordered list of pointers being transferred to the second buffer memory of the first type at a location pointed to by the head pointer;

burst transferring a contiguous data block from the packet memory to the second buffer memory using the ordered list of pointers in the second buffer memory when the packet size indicates the packet is long; and

buffering the contiguous data block transferred from the second buffer memory in an egress queue.

30. The method of claim 29 wherein the first type is a static random access memory and the second type is a synchronous dynamic random access memory.

31. The method of claim 29 wherein the input buffer memory and the second buffer memory have same sizes.

32. The method of claim 29 wherein the input buffer memory and the second buffer memory have different sizes.

33. A system comprising:

a channel in a network having an ingress and egress;

a data buffer circuit coupled to the channel to buffer data transmitted over the channel, the data buffer circuit comprising:

an input buffer memory of a first type to store data associated with a connection identifier corresponding to the channel, the data being organized into at least one chunk based on a linked list, the at least one chunk comprising at least one chunk data block, the connection identifier identifying a connection in the channel, the data being part of a data stream of a packet associated with the connection, the packet having a defined packet size,

an output buffer memory of the first type to store the data transferred from the input buffer memory, and

a packet memory of a second type coupled to the input and output buffer memories; and

a write circuit (i) to write the at least one chunk data block to the packet memory in response to a transfer condition if the packet size indicates the packet is long, and (ii) to write the at least one chunk data block to the output buffer memory in response to the transfer condition if the packet size indicates the packet is short.

34. The system of claim 33 wherein the data buffer circuit further comprises:

a descriptor memory to store descriptor information corresponding to the at least one chunk; and

a controller coupled to the descriptor memory and the input and output buffer memories to control data transfer between the buffer memories and the packet memory using the descriptor information.

35. The system of claim 34 wherein the at least one chunk further comprises:

a chunk header to store chunk information associated with the linked list.

36. The system of claim 35 wherein the chunk information includes at least one of a pointer to point to one other chunk, a size specifier to specify size of the at least one chunk, and a type specifier to specify type of the at least one chunk.

37. The system of claim 36 wherein the at least one chunk is one of a head chunk corresponding to one end of the data stream, a linking chunk corresponding to an intermediate portion of the data stream, and a tail chunk corresponding to one other end of the data stream.

38. The system of claim 37 wherein the descriptor information includes at least one of head and tail pointers, the head and tail pointers pointing to the head and tail chunks, respectively.

39. The system of claim 38 wherein the connection identifier points to one of the head and tail pointers.

40. The system of claim 34 wherein the controller comprises:

an ingress queue to buffer the data stream of the packet from the ingress of the channel; and

a queue segmenter to chunk the data stream into the at least one chunk.

41. The system of claim 40 wherein the input buffer memory stores the at least one chunk transferred from the queue segmenter.

42. The system of claim 41 wherein the input buffer memory comprises a queue associated with the connection identifier, the queue having a threshold and being configured to store the at least one chunk.

43. The system of claim 34 wherein the transfer condition includes at least one of an overflow of the threshold, the packet size, and a scheduled egress request.

44. The system of claim 43 wherein the controller further comprises:

a data combiner to combined the chunk data block of one chunk with the chunk data block of at least one other chunk in the input buffer memory;

wherein the write circuit (i) writes the combined chunk data block to the packet memory if the packet size indicates the packet is long, the combined chunk data block forming a contiguous data block in the packet memory, and (ii) writes the combined chunk data block to the output buffer memory if the packet size indicates the packet is short.

45. The system of claim 42 wherein the controller further comprises:

a list creator to create an ordered list of pointers associated with chunk headers of the one and the at least one other chunk, the ordered list of pointers being transferred to the output buffer memory of the first type at a location pointed to by a head pointer;

a read circuit to burst transfer the contiguous data block from the packet memory to the output buffer memory using the ordered list of pointers in the output buffer memory if the packet size indicates the packet is long; and

an egress queue to buffer the contiguous data block transferred from the output buffer memory.

46. The system of claim 45 wherein the input buffer memory and the output buffer memory have same sizes.

47. The system of claim 45 wherein the input buffer memory and the output buffer memory have different sizes.

48. The system of claim 45 wherein the first type is a static random access memory and the second type is a synchronous dynamic random access memory.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Mar 8, 2006
From: SILICON VALLEY BANK
To: ACORN NETWORKS, INC.
Reel/Frame 017262/0751 →
RELEASE Recorded Feb 27, 2006
From: SILICON VALLEY BANK
To: ACORN NETWORKS, INC.
Reel/Frame 017606/0084 →
RECORD TO CORRECT WRONG SERIAL NUMBER 09/688,407 ON A DOCUMENT PREVIOUSLY RECORDED ON REEL 014217/FRAME 0485 Recorded Aug 27, 2004
From: ACORN NETWORKS INC.
To: NAVY, UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF THE
Reel/Frame 015117/0615 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2003
From: CHU, TAM-ANH
To: NAVY, UNITED STATES OF AMERICA, AS REPRESENTED BY, THE SECRETARY OF THE
Reel/Frame 014586/0357 →
SECURITY INTEREST Recorded Dec 28, 2000
From: ACOM NETWORKS, INC.
To: SILICON VALLEY BANK
Reel/Frame 011390/0506 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2000
From: CHU, TAM-ANH
To: ACORN NETWORKS, INC.
Reel/Frame 011135/0181 →
Continuity (1)
Provisional Application 6015609800 · Sep 24, 1999