Self-adjusting, adaptive, minimal noise input amplifier circuit
View Patent ↗A self-adjusting adaptive input circuit with minimal excess noise and a linear charge-handling capacity exceeding 10 9 electrons to enable high-quality imaging at long wavelength infrared backgrounds and video frame rates is disclosed. An integration capacitor stores a charge produced from a photodetector. A self-adjusting current source skims a current during integration on the integration capacitor. The gate voltage of a skimming transistor is set via a programming transistor in order to set the skim level.
1. A photodetector amplifier circuit comprising:
a photodetector;
an input transistor connected to the photodetector;
an integration capacitor connected to an output of the input transistor; and
an adaptive skimming circuit connected to the integration capacitor, the adaptive skimming circuit comprising:
a current source transistor;
a programming capacitor connected to the current source transistor;
a programming transistor connected to the current source transistor and the programming capacitor;
a cascode transistor connected to the current source transistor and the input transistor;
a reset transistor connected to the input transistor; and
a kTC-noise reducing capacitor connected between the programming transistor and the programming capacitor.
2. The circuit of claim 1 , wherein the adaptive skimming circuit further comprises a trim capacitor connected to the current source transistor, the programming capacitor, and the programming transistor.
3. The circuit of claim 2 , further comprising an external voltage transistor connected to the programming transistor.
4. The circuit of claim 3 , further comprising a source follower transistor connected to the output of the input transistor.
5. The circuit of claim 3 , further comprising an access transistor connected between the input transistor and a bus.
6. The circuit of claim 5 , further comprising an external capacitor connected to the bus.
7. The circuit of claim 2 , further comprising a negative feedback amplifier connected between the photodetector and the input transistor, wherein the photodetector is a low impedance detector.
8. A pixel cell comprising:
an input transistor;
a photodetector coupled to the source of the input transistor;
an integration capacitor for storing a charge proportional to an amount of incident light on the photodetector; and
an adaptive skimming circuit formed in the pixel cell and connected only to the pixel cell comprising:
a current source transistor connected across the integration capacitor;
a cascode transistor connected to the current source transistor and the input transistor;
a reset transistor connected to the input transistor;
a programming capacitor connected to the current source transistor; and
a programming transistor connected to the current source transistor;
wherein a current source provided by the current source transistor sinks a set level of current during integration of a charge on the integration capacitor, such that a photodetector current is optimized at each pixel.
9. The pixel cell of claim 8 , wherein the adaptive skimming circuit further comprises a trim capacitor.
10. The pixel cell of claim 9 , wherein the adaptive skimming circuit further comprises a kTC-noise reducing capacitor connected between the programming transistor and the programming capacitor.
11. The pixel cell of claim 10 , further comprising an external voltage transistor connected to the programming transistor.
12. The pixel cell of claim 11 , further comprising a source follower transistor connected to the output of the input transistor.
13. The pixel cell of claim 11 , further comprising an access transistor connected between the input transistor and a bus.
14. The pixel cell of claim 13 , further comprising an external capacitor connected to the bus.
15. The pixel cell of claim 11 , further comprising a negative feedback amplifier connected between the photodetector and the input transistor, wherein the photodetector is a low impedance detector.
16. A focal plane array (FPA) having a plurality of pixel cells, each pixel cell comprising:
an input transistor;
a photodetector coupled to the source of the input transistor;
an integration capacitor for storing a charge proportional to an amount of incident light on the photodetector; and
an adaptive skimming circuit comprising:
a current source transistor connected across the integration capacitor;
a cascode transistor connected to the current source transistor and the input transistor;
a reset transistor connected to the input transistor;
a programming capacitor connected to the current source transistor;
a programming transistor connected to the current source transistor;
a trim capacitor connected to the programming transistor; and
a kTC-noise reducing capacitor connected between the programming transistor and the programming capacitor;
wherein a current source provided by the current source transistor skims off current during integration on the integration capacitor.
17. A method for skimming current in an amplifier circuit, the method comprising:
generating a signal proportional to an amount of light incident on a photodetector;
producing a sink current; and
reading out a signal that is proportional to the difference between the generated signal and the sink current;
wherein producing a sink current comprises:
setting a gate voltage of a skimming transistor by applying an enabling pulse to a programming transistor that produces a replicating current in the skimming transistor; and
applying a trimming voltage to a trimming capacitor.
18. The method of claim 17 , wherein further comprising storing the generated current into a capacitor, and reading out the signal from the capacitor, such that the sink current sinks a set level of a signal read out from the capacitor.
19. An amplifier circuit for coupling infrared (IR) detectors to multiplexing readouts, the circuit comprising:
an input transistor;
a detector coupled to a source of the input transistor;
a current source transistor having a drain connected to a drain of the input transistor;
an integration capacitor connected between the drain and a source of the current source transistor;
a programming capacitor connected between a gate and the source of the current source transistor;
a programming transistor having a drain connected to the drain of the current source transistor, and a source connected to the source of the current source transistor;
a trim capacitor connected to the source of the programming transistor and the gate of the current source transistor;
a kTC-noise reducing capacitor connected between the source of the programming transistor and the gate of the current source transistor.
20. The circuit of claim 19 , further comprising:
a reset transistor having a drain connected to the drain of the input transistor; and
a cascode transistor having a drain connected to the drain of the input transistor, and a source connected to a drain of the current source transistor.
21. The circuit of claim 20 , further comprising an external voltage transistor having a drain connected to the source of the programming transistor, and a source connected to an external voltage.
22. The circuit of claim 21 , further comprising a source follower transistor having a source connected to the drain of the input transistor.
23. The circuit of claim 22 , wherein the integration capacitor and the programming capacitor are formed from MOSFETs.