Compact active pixel with low-noise snapshot image formation
View Patent ↗A low-noise active pixel circuit is disclosed that efficiently suppresses reset (kTC) noise by using a compact preamplifier consisting of a photodetector and only four MOSFETs of identical polarity, in conjunction with ancillary circuits located on an imager's periphery. The supporting circuits help the simplified pixel circuit to synchronously acquire (i.e., take a snapshot) an image across an imaging array, read the signal with low noise, and efficiently reset the pixel with low noise.
1. An active pixel sensor circuit comprising:
a photodetector;
a reset transistor connected between the photodetector and a first bus;
a snapshot transistor having a node connected to the photodetector;
a driver transistor connected to a row driver bus and the snapshot transistor;
a row driver circuit connected to the row driver bus;
an isolation transistor connected between the driver transistor and a column bus; and
a column buffer connected to the column bus;
wherein the transistors are MOSFETs and a tapered reset signal is applied to the reset transistor in order to reset the photodetector, and wherein during a reset operation, the row driver circuit grounds the driver transistor such that at least a portion of the column buffer acts as a current source for a feedback amplifier formed by the driver transistor, isolation transistor, and the column buffer.
2. The active pixel sensor circuit of claim 1 , wherein a charge from the photodetector is transferred to a gate capacitance of the driver transistor via the snapshot transistor.
3. The active pixel sensor circuit of claim 2 , wherein the reset transistor discharges any charge left on the photodetector along with any charge on the gate of the driver transistor during a reset operation.
4. The active pixel sensor circuit of claim 3 , wherein the reset transistor is disabled during a signal integration mode and a snapshot image capture mode.
5. The active pixel sensor circuit of claim 4 , wherein, after snapshot image capture, the reset transistor is enabled in order to drain any unwanted charge that is generated after the integration mode.
6. A CMOS imager array circuit comprising:
a photodetector;
a reset MOSFET having a source connected to the photodetector, a gate connected to a reset input signal, and a drain connected to a first bus;
a snapshot MOSFET having a source connected to the photodetector and a gate connected to a snapshot signal;
a driver MOSFET having a drain connected to a row driver bus and a gate connected to a drain of the snapshot MOSFET;
a row driver circuit connected to the row driver bus;
an isolation MOSFET having a drain connected to a source of the driver MOSFET, a gate connected to an access signal, and a source connected to a column bus; and
a column buffer connected to the column bus;
wherein a tapered reset signal is applied to the reset MOSFET in order to reset the photodetector, and wherein during a reset operation, the row driver circuit grounds the driver transistor such that at least a portion of the column buffer acts as a current source for a feedback amplifier formed by the driver transistor, isolation transistor, and the column buffer.
7. The CMOS imager array circuit of claim 6 , wherein the row driver circuit and the column buffer are shared among a plurality of pixel circuits.
8. The imager array of claim 7 , wherein the reset, snapshot, driver and isolation MOSFETs are all of the same polarity.
9. The CMOS imager array of claim 8 , wherein a charge from the photodetector is transferred to a gate capacitance of the driver MOSFET via the snapshot MOSFET.
10. The CMOS imager array of claim 9 , wherein the reset MOSFET discharges any charge left on the photodetector along with any charge on the gate of the driver MOSFET during a reset operation.
11. The CMOS imager array of claim 10 , wherein the reset MOSFET is disabled during a signal integration mode and a snapshot image capture mode.
12. The CMOS imager array of claim 11 , wherein, after snapshot image capture, the reset MOSFET is enabled in order to drain any unwanted charge that is generated after the integration mode.