Architecture for implementing virtual multiqueue fifos

1. A circuit configured to provide a storage element comprising one or more virtual multiqueue FIFOs, wherein said circuit is configured to (i) detect a fastest one of a plurality of clocks and (ii) operate said storage element in a single clock domain corresponding to said fastest one of said plurality of clocks.

2. The circuit according to claim 1 , wherein said circuit is further configured to control said one or more virtual multiqueue FIFOs.

3. The circuit according to claim 2 , wherein said circuit is further configured to control a size of each of a plurality of queues.

4. The circuit according to claim 2 , wherein said circuit is further configured to control a number of queues within said one or more virtual multiqueue FIFOs.

5. The circuit according to claim 1 , wherein said circuit is further configured to synchronize a read and a write operation to at least one of said plurality of clocks.

6. The circuit according to claim 1 , further comprising:

a read interface configured to synchronize a read of said storage element; and

a write interface configured to synchronize a write of said storage element.

7. The circuit according to claim 6 , wherein said read and said write interfaces are further configured in response to one or more control signals.

8. The circuit according to claim 1 , further comprising:

a clock detect and configure circuit configured to (i) receive said plurality of clocks and (ii) control said storage element.

9. The circuit according to claim 8 , wherein said clock detect and configure circuit is further configured to clock said storage element.

10. The circuit according to claim 8 , wherein said plurality of clocks comprises a write clock signal and a read clock signal.

11. The circuit according to claim 1 , wherein said storage element comprises a single port memory.

12. The circuit according to claim 1 , wherein said storage element comprises a dual port memory.

13. The circuit according to claim 1 , further comprising:

a control circuit configured to control said one or more virtual multiqueue FIFOs.

14. The circuit according to claim 13 , wherein said control circuit comprises:

a control arbitration, flag and address generation logic circuit.

15. The circuit according to claim 13 , wherein said control circuit comprises:

a control arbitration, and flag generation circuit; and

an address generation block comprising (i) a FIFO address to physical address generator circuit, (ii) a FIFO pointer storage element for storing FIFO related information and (iii) a forward pointer storage element for maintaining link-lists for the virtual multiqueue FIFO, wherein said address generation logic communicates with gain control arbitration flag logic.

16. And apparatus comprising:

means for storing data within a storage device comprising one or more virtual multiqueue FIFOs; and

means for detecting a fastest one of a plurality of clocks and operating said data storing means in a single clock domain corresponding to said fastest one of said plurality of clocks.

17. A method for implementing one or more virtual multiqueue FIFOs comprising the steps of:

(A) storing data within a storage device comprising said one or more virtual multiqueue FIFOs;

(B) detecting a fastest one of a plurality of clocks; and

(C) operating said storage device in a single clock domain corresponding to said fastest one of said plurality of clocks.

18. The method according to claim 17 , further comprising the step of:

controlling said one or more virtual multiqueue FIFOs.

19. The method according to claim 18 , wherein said controlling step comprises controlling a size of each of a plurality of queues within said one or more virtual multiqueue FIFOs.

20. The method according to claim 18 , wherein said controlling step comprises controlling a number of queues within said one or more virtual multiqueue FIFOs.