Charge transfer device for increasing data rate and reducing power consumption

1. A charge transfer device comprising:

a semiconductor substrate;

a charge transfer path formed in said semiconductor substrate and made of a first conductivity type semiconductor layer, said charge transfer path having first barrier layers having a high potential and first well layers having a low potential, disposed alternately;

a plurality of first and second charge transfer electrodes alternately formed near above the first barrier layers and first well layers of said charge transfer path;

a plurality of charge transfer electrode pairs each having adjacent first and second two charge transfer electrodes connected together;

a third pulse signal generator circuit for applying either a fourth pulse signal train of two-phase for 2-phase driving of charges in said charge transfer path to two charge transfer electrode pairs or a fifth pulse signal train for 2k-phase driving or more of charges in said charge transfer path to the charge transfer electrode pairs;

a charge storage region formed adjacent to a final stage of the charge transfer electrodes for temporarily storing charges transferred in said charge transfer path; and

a charge detecting region for detecting an amount of charges stored in said charge storage region.

2. A charge transfer device according to claim 1 , wherein said charge storage region comprises:

a second barrier layer and a second well layer formed adjacent to each other in said charge transfer path;

a third charge transfer electrode and a fourth charge transfer electrode formed above the second barrier layer and the second well layer; and

a stored charge output pulse generator circuit connected to said third charge transfer electrode and said fourth charge transfer electrode, for generating a stored charge output pulse.

3. A charge transfer device according to claim 1 , wherein the second well layer has an electric capacity larger than an electric capacity of the first well layer and the channel transfer device further comprises a floating diffusion region formed adjacent to the second well layer for detecting an amount of charges transferred from said charge transfer path.

4. A charge transfer device according to claim 1 , further comprising a horizontal charge transfer path and the third pulse signal generator circuit applies either a fourth pulse signal train of two-phase for 2-phase driving of charges in said horizontal charge transfer path or a fifth pulse signal train for 2k-phase driving or more of charges in said horizontal charge transfer path.

5. A charge transfer device comprising:

a semiconductor substrate;

a charge transfer path formed in said semiconductor substrate and made of a first conductivity type semiconductor layer;

a plurality of charge transfer electrodes formed near above said charge transfer path; and

a first pulse signal generator circuit for applying either a first pulse signal train for n-phase (n being an integer larger than 1) driving of charges in said charge transfer path to said charge transfer electrodes or a second pulse signal train for (n+1)-phase driving of charges in said charge transfer path to said charge transfer electrodes;

a charge storage region formed adjacent to a final stage of the charge transfer electrodes for temporarily storing charges transferred in said charge transfer path; and

a charge detecting region for detecting an amount of charges stored in said charge storage region.

6. A charge transfer device according to claim 5 , further comprising a horizontal charge transfer path and the first pulse signal generator circuit applies either a first pulse signal train for n-phase (n being an integer larger than 1) driving of charges in said horizontal charge transfer path or a second pulse signal train for (n+1)-phase driving of charges in said horizontal charge transfer path.

7. A charge transfer device comprising:

a semiconductor substrate;

a charge transfer path formed in said semiconductor substrate and made of a first conductivity type semiconductor layer;

a plurality of charge transfer electrodes formed near above said charge transfer path; and

a second pulse signal generator circuit for applying either a first pulse signal train for n-phase driving (n being an integer larger than 1) of charges in said charge transfer path to said charge transfer electrodes or a third pulse signal train for (n×m)-phase driving (m being an integer larger than 1) of charges in said charge transfer path to said charge transfer electrodes;

a charge storage region formed adjacent to a final stage of the charge transfer electrodes for temporarily storing charges transferred in said charge transfer path; and

a charge detecting region for detecting an amount of charges stored in said charge storage region.

8. A charge transfer device according to claim 7 , further comprising a horizontal charge transfer path and the second pulse signal generator circuit applies either a first pulse signal train for n-phase driving (n being an integer larger than 1) of charges in said horizontal charge transfer path or a third pulse signal train for (n×m)-phase driving (m being an integer larger than 1) of charges in said horizontal charge transfer path.

9. A charge transfer device comprising:

a semiconductor substrate;

a charge transfer path formed in said semiconductor substrate and made of a first conductivity type semiconductor layer, said charge transfer path having first barrier layers and second well layers alternately disposed adjacent to each other;

a plurality of charge transfer electrodes formed adjacent to each other above said charge transfer path;

a second pulse signal generator circuit for applying either a first pulse signal train for n-phase driving (n being an integer larger than 1) of charges in said charge transfer path to said charge transfer electrodes or a third pulse signal train for (n×m)-phase driving (m being an integer larger than 1) of charges in said charge transfer path to said charge transfer electrodes;

a charge storage region formed adjacent to a final stage of the charge transfer electrodes for temporarily storing charges transferred in said charge transfer path; and

a charge detecting region for detecting an amount of charges stored in said charge storage region,

wherein said charge storage region comprises:

a second barrier layer and a second well layer formed adjacent to each other in said charge transfer path;

a third charge transfer electrode and a fourth charge transfer electrode formed above the second barrier layer and the second well layer; and

a stored charge output pulse generator circuit connected to said third charge transfer electrode and said fourth charge transfer electrode, for generating a stored charge output pulse, and

wherein an electric capacity of the second well layer has an electric capacity by (n×m−3) times or more larger than an electric capacity of the first well.