Image sensor with improved dynamic range by applying negative voltage to unit pixel

1. An image sensor comprising:

a semiconductor substrate of a first conductivity type;

a peripheral circuit formed on a first region of the semiconductor substrate, wherein a ground voltage level is applied to the first region;

a unit pixel array having a plurality of unit pixels formed on a second region of the semiconductor substrate, wherein the first region is isolated from the second region and wherein a negative voltage level is applied to the second region;

a buried layer isolating each of the unit pixels so that the buried layer surrounds each of the unit pixels; and

a negative voltage circuit configured to provide the negative voltage for the second region,

wherein the semiconductor substrate comprises a P+-type substrate and a P-type epitaxial layer that is formed in the P+-type substrate,

wherein the buried layer is formed in the P-type epitaxial layer,

wherein the negative voltage circuit comprises a P+ diffusion layer that is formed in the P-type epitaxial layer and wherein the negative voltage is applied to the P+ diffusion layer.

2. The image sensor as recited in claim 1 , wherein the P+ diffusion layer is shared with the second region of neighboring pixels.

3. An image sensor, comprising:

a plurality of unit pixels formed in a first region of a substrate that is biased at a ground reference, each pixel surrounded by a first epitaxial layer that is biased at a negative potential relative to the ground reference; and

a bias generator formed in a second region of the substrate that is biased to the ground reference,

wherein the substrate comprises a P+-type substrate and the first epitaxial layer is a P-type epitaxial layer that is formed in the P+-type substrate,

wherein a buried layer surrounds the first epitaxial layer,

wherein the bias generator comprises a P+ diffusion layer that is formed in the P-type epitaxial layer and wherein the negative potential is applied to the P+ diffusion layer.

4. A method of improving the charge transfer efficiency of a photodiode device, the method comprising the steps of:

providing a ground reference in a first region formed in a substrate;

providing a bias generator in the first region for generating a negative potential relative to the ground reference;

providing a photodiode device in a second region formed in the substrate including spacing apart the first region and the second region and isolating the second region from the first region, the photodiode device having a photodiode including a p-type side that is electrically coupled to the negative potential, wherein the substrate comprises a P+-type substrate and the photodiode is disposed in a P-type epitaxial layer that is formed in the P+-type substrate; and

providing a buried layer that surrounds the P-type epitaxial layer,

wherein the bias generator comprises a P+ diffusion layer that is formed in the P-type epitaxial layer and wherein the negative potential is applied to the P+ diffusion layer.