Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument
View Patent ↗A semiconductor device comprising: a semiconductor element ( 10 ) having a plurality of electrodes ( 12 ); an interconnect pattern ( 20 ) electrically connected to the electrodes ( 12 ); a plurality of laminated insulating layers ( 41, 42 and 43 ); and a plurality of external terminals ( 30 ) electrically connected to the interconnect pattern ( 20 ). A plurality of holes ( 44, 46 , and 48 ) are respectively formed in the insulating layers ( 41, 42 , and 43 ) to form an opening portion ( 40 ) communicating from the hole ( 48 ) in the highest insulating layer ( 43 ) to the hole ( 44 ) in the lowest insulating layer ( 41 ). An external terminal ( 30 ) is provided within the opening portion ( 40 ), and the second hole ( 46 ) formed in the higher positioned second insulating layer ( 42 ) is larger than the first hole ( 44 ) formed in the lower positioned first insulating layer ( 41 ).
1. A semiconductor device comprising:
a semiconductor element having a plurality of electrodes,
an interconnect pattern electrically connected to the electrodes,
external terminals electrically connected to the interconnect pattern, each of the external terminals not overlapping with any one of the electrodes, and
a plurality of insulating layers formed around the external terminals, the insulating layers including a first layer, the insulating layers including a second layer formed closer to the semiconductor element than the first layer,
wherein the interconnect pattern is formed between the semiconductor element and the plurality of insulating layers,
wherein the second layer contacts the interconnect pattern, and the first layer does not contact the interconnect pattern,
wherein the coefficient of thermal expansion of the first layer is greater than the coefficient of thermal expansion of the second layer.
2. The semiconductor device as defined in claim 1 ,
wherein at least one of the plurality of insulating layers has a stress relieving function.
3. The semiconductor device as defined in claim 1 ,
wherein at least one of the plurality of insulating layers is formed of a resin.
4. The semiconductor device as defined in claim 1 ,
wherein the insulating layers contact the external terminals at opening portions each of which has an inclined surface providing a taper increasing in size from the second layer to the first layer.
5. The semiconductor device as defined in claim 1 ,
wherein each of the external terminals includes a base and a connection portion provided on the base; and
wherein the base is provided in an opening portion through which each of the external terminals contact the insulating layers.
6. The semiconductor device as defined in claim 1 ,
wherein the insulating layers contact the external terminals at opening portions each of which is formed with a curved surface.
7. The semiconductor device as defined in claim 1 ,
wherein the interconnect pattern is formed on a stress relieving layer formed below the plurality of insulating layers.
8. The semiconductor device as defined in claim 1 ,
wherein the uppermost layer of the insulating layers is formed over the whole surface of a layer just under the uppermost layer, the uppermost layer formed in a region except for an area of the external terminals.
9. The semiconductor device as defined in claim 1 ,
wherein the uppermost layer of the insulating layers has its area smaller than an area of a layer just under the uppermost layer.
10. A semiconductor device comprising:
a semiconductor element having a plurality of electrodes;
an interconnect pattern electrically connected to the electrodes;
external terminals electrically connected to the interconnect pattern, each of the external terminals not overlapping with any one of the electrodes; and
a plurality of insulating layers formed around the external terminals, the insulating layers including a first layer, the insulating layers including a second layer formed closer to the semiconductor element than the first layer;
wherein the interconnect pattern is formed between the semiconductor element and the plurality of insulating layers;
wherein the second layer contacts the interconnect pattern and the first layer does not contact the interconnect pattern;
wherein the Young's modulus of the second layer is greater than the Young's modulus of the first layer.
11. The semiconductor device as defined in claim 10 ,
wherein at least one of the plurality of insulating layers has a stress relieving function.
12. The semiconductor device as defined in claim 10 ,
wherein at least one of the plurality of insulating layers is formed of a resin.
13. The semiconductor device as defined in claim 10 ,
wherein the insulating layers contact the external terminals at opening portions each of which has an inclined surface providing a taper increasing in size from the second layer to the first layer.
14. The semiconductor device as defined in claim 10 ,
wherein each of the external terminals includes a base and a connection portion provided on the base; and
wherein the base is provided in an opening portion through which each of the external terminals contact the insulating layers.
15. The semiconductor device as defined in claim 10 ,
wherein the insulating layers contact the external terminals at opening portions each of which is formed with a curved surface.
16. The semiconductor device as defined in claim 10 ,
wherein the interconnect pattern is formed on a stress relieving layer formed below the plurality of insulating layers.
17. The semiconductor device as defined in claim 10 ,
wherein the uppermost layer of the insulating layers is formed over the whole surface of a layer just under the uppermost layer, the uppermost layer formed in a region except for an area of the external terminals.
18. The semiconductor device as defined in claim 10 ,
wherein the uppermost layer of the insulating layers has its area smaller than an area of a layer just under the uppermost layer.