IP Library Granted Patent US 6,868,481
Granted Patent B1
US 6,868,481 · App. 09/704,176 · Granted Mar 15, 2005

Cache coherence protocol for a multiple bus multiprocessor system

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Quick Facts
Patent No.
US 6,868,481
App. No.
09/704,176
Granted
Mar 15, 2005
Kind
B1
Abstract

A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, so that every device that can request a copy of memory data maintains a local copy of the GOTL. The GOTL can be limited to a relatively small size. For a limited size list, a tag may need to be evicted to make room for a new tag. A line associated with an evicted tag must be written back to memory.

Claims (22)

1. A computer system comprising:

a plurality of memory caches;

a list containing;

an address reference for every line in the plurality of memory caches for which a corresponding line in memory may not be identical; and

an indicator of which cache owns each line; and

the list not containing;

address references for lines that are shared or uncached; and

data corresponding to the address references.

2. The computer system of claim 1 wherein the address reference is a tag.

3. The computer system of claim 1 , wherein the number of address references that the list can hold is substantially less than the total number of lines that can be stored in the plurality of memory caches.

4. The computer system of claim 1 , wherein the list comprises a single list shared by all devices in the computer system.

5. The computer system of claim 1 , wherein every device that can request a copy of memory data maintains a local copy of the list.

6. A method for maintaining cache coherency in a computer system, comprising:

entering into a list, an address reference for all lines that are owned;

not entering into the list address references for lines that are shared or uncached;

updating the list only when ownership of a line changes; and

removing an address reference to a line, from the list, when the line has remained in the list for longer than a specified time.

7. A method for maintaining cache coherency in a computer system, comprising:

entering into a list, an address reference for all lines that are owned;

not entering into the list address references for lines that are shared or uncached;

updating the list only when ownership of a line changes; and

removing an address reference to a line, from the list, even when the list is not full, to help prevent the list from filling.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2021
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 056157/0492 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →