IP Library Granted Patent US 6,975,189
Granted Patent B1
US 6,975,189 · App. 09/705,134 · Granted Dec 13, 2005

On-chip multilayer metal shielded transmission line

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Quick Facts
Patent No.
US 6,975,189
App. No.
09/705,134
Granted
Dec 13, 2005
Kind
B1
Abstract

Multi-layer metal-shielded monolithic transmission lines are formed in side-by-side arrangement by depositing parallel planar thin film, conductive layers, separated by nonconductive separator layers to form a stack of alternating conductive and nonconductive layers. The conductive layers form a top and a bottom conductive plane and establish a mutually registered selected width of the stack. A center conductive layer has laterally spaced apart conductive strips separated by nonconductive spacer layers. The two laterally terminal of the conductive strips are spaced at the selected width. Each of the nonconductive separator layers provides a plurality of elongated vias between the two lateral terminals of the three conductive strips and the conductive planes. The vias are filled as each next metal deposition is applied for electrically interconnecting the conductive strips and planes so as to form a monolithic conductive shield about the centermost signal carrying conductor of the three conductive strips, providing electrical isolation in a coaxial arrangement.

Claims (15)

1. In the environment of a chip having a plurality of circuit elements, an on-chip multi-layer metal-shielded monolithic transmission line for connecting one of said plurality of circuit elements to another of said plurality of circuit elements, said on-chip multi-layer metal-shielded monolithic transmission line comprising:

a plurality of parallel planar thin film conductive layers; and

a plurality of planar thin film nonconductive separator layers disposed such that each adjacent pair of the conductive layers is separated by at least one of said plurality of planar thin film nonconductive layers to provide a stack of alternating conductive and nonconductive layers,

wherein an initial one and a final one of said conductive layers provide a top conductive plane and a bottom conductive plane,

wherein a center one of the conductive layers comprises three laterally spaced apart conductive strips, said conductive strips separated by nonconductive material such that two laterally spaced terminal strips of the three conductive strips are spaced at a selected width from the center conductive strip thereof,

wherein each of the nonconductive separator layers include a plurality of vias between the two laterally spaced terminal conductive strips of the three conductive strips and the top and bottom conductive planes, said plurality of vias filled with conductive material.

2. The invention of claim 1 , wherein the center conductive strip provides an electrical signal carrying path.

3. A chip having a plurality of on-chip multi-layer metal-shielded monolithic transmission lines comprising:

a plurality of parallel planar thin film conductive layers, each adjacent pair of the conductive layers separated by at least one of a plurality of planar thin film nonconductive separator layers to provide a stack of alternating conductive and nonconductive said layers,

wherein an initial one and a final one of said conductive layers providing a top conductive plane and a bottom conductive plane,

wherein one of the conductive layers between the top and the bottom conductive planes includes a plurality of N laterally spaced apart conductive strips, where N is an odd integer,

wherein each laterally adjacent pair of the conductive strips are separated at a predetermined width by nonconductive material,

wherein the plurality of nonconductive separator layers include a plurality of metal filled vias positioned for electrically interconnecting every other one of the laterally spaced apart conductive strips to the top an bottom conductive planes,

wherein the distance between top conductive plane and bottom conductive plane is substantially equal to the distance between every other laterally spaced conductive strips, and

wherein the plurality of vias of one of the transmission lines are staggered relative to the plurality of vias of an adjacent one of the transmission lines so as to preclude an electromagnetic line of sight path between the signal carrying conductive strips of the transmission lines.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2009
From: TELASIC COMMUNICATIONS, INC.
To: MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 022939/0399 →
RELEASE Recorded Oct 16, 2008
From: SILICON VALLEY BANK
To: TELASIC COMMUNICATIONS INC.
Reel/Frame 021691/0567 →
SECURITY INTEREST Recorded Aug 26, 2002
From: TELASIC COMMUNICATIONS, INC.
To: SILICON VALLEY BANK
Reel/Frame 013169/0107 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2002
From: RAYTHEON COMPANY
To: TELASIC COMMUNICATIONS, INC.
Reel/Frame 013107/0275 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2001
From: REAMON, ALAN E.; LINDER, LLOYD; HIRATA, ERICK M.; ELMI, NICK
To: RAYTHEON COMPANY
Reel/Frame 011745/0428 →