Fabrication and controlled release of structures using etch-stop trenches
MEMS structures may be formed on a substrate by forming a series trenches filled with etch-stop material in the device layer, followed by an isotropic etch of the device material stopping on the etch-stop material. This approach provides a controlled release method where the exact timing of the isotropic release etch becomes non-critical. Further, using this method, structures with significant topology may be fabricated while keeping the wafer topology to a minimum during processing until the very end of the process. Using the method of this invention, features with large topology may be formed while keeping the wafer topology to a minimum until the very end of the process.
1. A method for a controlled release of structures comprising:
a) forming one or more trenches in a layer of device material;
b) filling one or more selected trenches with an etch-stop material to form one or more etch-stop trenches;
c) defining one or more structures between the selected trenches;
d) forming a structural layer proximate one or more exposed areas of the device layer, wherein the structural layer includes one or more structures that are formed directly on top of an etch-stop layer; and
e) etching one or more portions of the device layer between the etch-stop trenches to release the structures, wherein the etching does not etch the etch-stop material.
2. The method of claim 1 , wherein b) includes depositing etch-stop material over the surface of the device layer.
3. The method of claim 2 wherein c) includes forming one or more openings in the etch-stop material that has been deposited over the surface of the device layer.
4. The method of claim 2 , wherein the etching undercuts one or more portions of the etch-stop material that has been deposited over the surface of the device layer.
5. The method of claim 1 where the layer of device material is disposed between two layers of etch-stop material.
6. The method of claim 1 , wherein the device layer includes one or more layers of a silicon-on-insulator (SOI) substrate.
7. The method of claim 1 , wherein the device layer is a layer of glass, quartz or oxide.
8. The method of claim 1 , wherein e includes a wet etch process.
9. The method of claim 1 , wherein e includes a dry etch process.
10. The method of claim 1 , wherein the etch process in e does not etch the structural layer.
11. The method of claim 1 , further comprising releasing one or more portions of the structural layer.
12. The method of claim 1 , wherein the etch process in e releases one or more portions of the structural layer.
13. The method of claim 1 , wherein the structural layer contains two or more sub-layers.
14. A process for forming structures comprising:
i) forming one or more trenches in a layer of device material;
ii) filling one or more selected trenches with an etch-stop material to form one or more etch-stop trenches;
iii) masking a surface of the layer of device material to expose one or more selected areas of device material that border one or more of the etch-stop trenches; and
iv) forming one or more structures on one or more of the selected areas of the device material that were exposed; and
v) etching one or more of the selected areas of the device layer to release the structures, wherein the etching does not etch the etch-stop material.
15. The method of claim 1 , wherein the structural layer is protected by one or more etch-stop layers.
16. The method of claim 14 , wherein one or more of the structures include a device layer protected by one or more etch-stop layers.
17. The method of claim 14 , wherein filling one or more selected trenches with an etch-stop material includes depositing etch-stop material over the surface of the device layer.
18. The method of claim 17 wherein masking a surface of the layer of device material includes forming one or more openings in the etch-stop material that has been deposited over the surface of the device layer.
19. The method of claim 17 , wherein the etching one or more of the selected areas of the device layer undercuts one or more portions of the etch-stop material that has been deposited over the surface of the device layer.
20. The method of claim 14 , where the layer of device material is disposed between two layers of etch-stop material.
21. The method of claim 14 , wherein the device material includes one or more layers of a silicon-on-insulator (SOI) substrate.
22. The method of claim 14 , wherein the device material includes glass, quartz or oxide.
23. The method of claim 14 , wherein etching one or more of the selected areas of the device layer includes a dry etch or wet etch process.
24. The method of claim 14 , wherein etching one or more of the selected areas of the device layer does not etch the structures.
25. The method of claim 24 , wherein the structures include two or more sub-layers.