On the fly data transfer between RGB and YCrCb color spaces for DCT interface
View Patent ↗A method for transferring data on the fly between an RGB color space and a YCrCb color space useful for a DCT block-computation engine significantly increases throughput and decreases processor overhead. According to one example embodiment, data is transferred from an RBG color space memory to a YCrCb color space memory in a form useful for presentation to a DCT block-computation engine. In response to accessing the RBG color space memory, the RBG values are asynchronously written to YCrCb intermediate buffers so that one of the YCrCb intermediate buffers is filled through sub-sampling in a manner useful for the DCT block-computation engine while another of the YCrCb intermediate buffers is still being filled. The DCT block-computation engine then accessed the filled YCrCb intermediate buffers while the other of the YCrCb intermediate buffers continues to collect RGB values from the RGB color space memory for the next DCT computation. Other aspects are directed to conversion of the RGB color space to the YCrCb color space using, respectively, a block-by-block conversion, a line-by-line conversion, and a word-by-word conversion.
1. A method for transferring data between an RGB color space memory and a YCrCb color space memory useful for presentation to a DCT block-computation engine, the method comprising:
providing at least two YCrCb intermediate buffers for storing data being transferred between the color space memories; and
using the DCT block-computation engine to access data in one of the YCrCb intermediate buffers while using the other of the YCrCb intermediate buffers for data accesses of the RGB color space memory.
2. The method of claim 1 , further including providing at least two RGB intermediate buffers for storing data being transferred between at least one of the YCrCb intermediate buffers and the RGB color space memory.
3. The method of claim 1 , further including converting data between the RGB color space memory and the YCrCb color space memory block by block.
4. The method of claim 1 , further including converting data between the RGB color space memory and the YCrCb color space memory line by line.
5. The method of claim 1 , further including converting data between the RGB color space memory and the YCrCb color space memory word by word.
6. The method of claim 1 , wherein the RGB data for a DCT in the YCrCb color space memory is four eight by eight Y arrays, one eight by eight Cr array and one eight by eight Cb array.
7. The method of claim 1 , further including compressing the transferred data in the YCrCb color space memory.
8. The method of claim 1 , further including decompressing the data in the YCrCb color space memory before using the DCT block-computation engine to access data stored in one of the YCrCb intermediate buffers.
9. A circuit arrangement for transferring data between an RGB color space memory and a YCrCb color space memory useful for presentation to a DCT block-computation engine, comprising:
at least two YCrCb intermediate buffers adapted for storing data being transferred between the color space memories; and
means for using the DCT block-computation engine to access data in one of the YCrCb intermediate buffers while using the other of the YCrCb intermediate buffers for data accesses of the RGB color space memory.
10. A circuit arrangement for transferring data between an RGB color space memory and a YCrCb color space memory useful for presentation to a DCT block-computation engine, comprising:
a DCT block-computation engine;
at least two YCrCb intermediate buffers for storing data being transferred between the color space memories; and
logic circuitry adapted to communicate data between the DCT block-computation engine data and one of the YCrCb intermediate buffers while using the other of the YCrCb intermediate buffers for data accesses of the RGB color space memory.
11. The circuit arrangement of claim 10 , further including a processor programmed to convert data in the RGB color space memory to the YCrCb color space memory block by block.
12. The circuit arrangement of claim 10 , further including a processor programmed to convert data in the RGB color space memory to the YCrCb color space memory line by line.
13. The circuit arrangement of claim 10 , further including a processor programmed to convert data in the RGB color space memory to the YCrCb color space memory using word by word.
14. The circuit arrangement of claim 10 , further including an RGB intermediate buffer for storing data being transferred between at least one of the YCrCb intermediate buffers and the RGB color space memory.
15. The circuit arrangement of claim 10 , further including a second RGB intermediate buffer for storing data being transferred between at least one of the YCrCb intermediate buffers and the RGB color space memory.
16. The circuit arrangement of claim 10 , further including an SDRAM configured and arranged to present RGB values from the RGB color space memory of the YCrCb intermediate buffers in multi-byte bursts.
17. The circuit arrangement of claim 10 , wherein said at least two YCrCb intermediate buffers for storing data being transferred between the color space memories includes a Y intermediate buffer, a Cr intermediate buffer, and a Cb intermediate buffer.
18. The circuit arrangement of claim 10 , wherein the logic circuitry includes an address calculator adapted to generate selected addresses for RGB values in the RGB color space memory, the selected addresses for the RGB values corresponding to noncontiguous memory locations in the RGB color space memory.