IP Library Granted Patent US 7,103,070
Granted Patent B2
US 7,103,070 · App. 09/730,679 · Granted Sep 5, 2006

Transmission system comprising a station of a first type and a station of a second type and synchronization method

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Quick Facts
Patent No.
US 7,103,070
App. No.
09/730,679
Granted
Sep 5, 2006
Kind
B2
Abstract

This transmission system comprises a station of a first type and a plurality of stations of a second type which include a transmitting part having a transmit timing controller for transmitting data at a transmit timing and a receiving part having synchronizing circuits for synchronization with data transmitted from the station of the first type. When the stations of the second type are moving, their transmit timing is modified to facilitate the synchronization of the reception of the station by solely being based on the receive timing at these stations of the second type.

Claims (9)

1. A synchronization method suitable for a system comprising at least a station of first type and a station of a second type, both of which include a transmitting part capable of transmitting data at a transmit timing and a receiving part capable of synchronizing data transmitted from stations to provide a receive timing, characterized in that the method comprises the following steps:

providing the receiving part of the station of the second type with a synchronization circuit that generates chip fractions shifted in time,

measuring a receive clock deviation made at the stations of the second type, and

adjusting a transmit clock at the station of the second type by adopting the opposite deviation value to compensate for a frequency shift due to a movement of the station of the second type.

2. A method as claimed in claim 1 , wherein the synchronization circuit provides chip fractions shifted in time produces a first output corresponding to a satisfactory state of synchronism.

3. A method as claimed in claim 2 , wherein the synchronization circuit provides chip fractions shifted in time produces an already produced chip fraction output that contains chip fraction previously produced at the first output.

4. A method as claimed in claim 3 , wherein the synchronization circuit provides chip fractions shifted in time produces a recently produced chip fraction output that contains chip fraction tat have just been produced.

5. A method as claimed in claim 4 , wherein the receiving part of the station of the second type further comprises an analysis circuit receives chip fractions shifted in time by the synchronization circuit and determines a frequency drift, therefrom.

6. A method as claimed in claim 5 , wherein the receiving part of the station of the second type further comprises means for modifying clock frequencies in response to the frequency drift.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2018
From: UNILOC LUXEMBOURG S.A.
To: UNILOC 2017 LLC
Reel/Frame 046532/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2018
From: PENDRAGON WIRELESS LLC
To: UNILOC LUXEMBOURG S.A.
Reel/Frame 045338/0601 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2012
From: IPG ELECTRONICS 503 LIMITED
To: PENDRAGON WIRELESS LLC
Reel/Frame 028594/0224 →