Method for recovering a clock signal in a telecommunications system and circuit thereof
View Patent ↗Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other. According to the invention, said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time, and, moreover, it is provided for selecting the recovered clock signal among said delayed clock signals.
1. A method for recovering a clock signal from an input data signal in a telecommunications system, the method comprising:
comparing said input data signal with a recovered clock signal in order to control a recovered clock signal generation;
generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other;
selecting said recovered clock signal among said delayed clock signals;
employing a number of delayed signals, such that a sum of shifts associated with said delayed signals covers a bit period of said input data signal; and dynamically changing said number of delayed signals by comparing said bit period with said sum of shifts;
wherein said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time.
2. The method according to claim 1 , wherein a shift between each adjacent pair of delayed signals is nominally equal.
3. The method according to claim 1 , further comprising obtaining said plurality of delayed clock signals by multi-delaying a single sole reference signal.
4. The method according to claim 2 , further comprising selecting a first recovery signal and a second signal before selecting said recovered clock signal.
5. The method according to claim 4 , further comprising switching between said first recovery signal and said second recovery signal for selecting said recovered clock signal.
6. The method according to claim 4 , further comprising shifting said first recovery signal and said second recovery signal by one time interval.
7. The method according to claim 5 , further comprising shifting said first recovery signal and said second recovery signal by one time interval.
8. The method according to claim 4 , further comprising providing enabling signals for activating switching between said first recovery signal and said second recovery signal.
9. A method for recovering a clock signal from an input data signal in a telecommunications system, the method comprising:
comparing said input data signal with a recovered clock signal in order to control a recovered clock signal generation;
generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other;
selecting said recovered clock signal among said delayed clock signals;
employing a number of delayed signals, such that a sum of shifts associated with said delayed signals covers a bit period of said input data signal;
performing a comparison operation which includes comparing said input data signal with said recovered clock signal, by using a comparison of several phases of at least one of said input data signal and said recovered clock signal, so as to obtain a plurality of samples for each sampling cycle; and
filtering an output of said comparison operation;
wherein said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time.
10. A circuit for recovering a clock signal from an input data signal in a telecommunications network, comprising:
a generating means configured to generate a recovery clock signal; and
a phase comparator configured to compare said input data signal phase and said recovery clock signal phase for supplying a phase information, which controls said generating means of said recovery clock signal; and
a selection means;
wherein said generating means further comprises a delay line having a plurality of taps for generating a plurality of delayed signals;
wherein a sum of shifts associated with said delayed signals covers a bit period of said input data signal; and
wherein said selection means comprises:
a selection block for selecting a first recovery signal and a second recovery signal from said plurality of delayed signals; and
a switch block for switching between said first recovery signal and said second recovery signal.
11. A circuit for recovering a clock signal from an input data signal in a telecommunications network, comprising:
a generating means configured to generate a recovery clock signal; and
a phase comparator configured to compare said input data signal phase and said recovery clock signal phase for supplying a phase information, which controls said generating means of said recovery clock signal;
wherein said generating means further comprises a delay line having a plurality of taps for generating a plurality of delayed signals;
wherein a sum of shifts associated with said delayed signals covers a bit period of said input data signal;
wherein said generating means comprises a selection means of said recovered clock signal;
wherein said selection means further comprises a control logic driving a selection block and a switch block according to said phase information supplied by said phase comparator; and
wherein said control logic comprises a filter for filtering said phase information.
12. A circuit for recovering a clock signal from an input data signal in a telecommunications network, comprising:
a generating means configured to generate a recovery clock signal; and
a phase comparator configured to compare said input data signal phase and said recovery clock signal phase for supplying a phase information, which controls said generating means of said recovery clock signal;
wherein said generating means further comprises a delay line having a plurality of taps for generating a plurality of delayed signals;
wherein a sum of shifts associated with said delayed signals covers a bit period of said input data signal;
wherein said generating means comprises a selection means of said recovered clock signal;
wherein said selection means further comprises a control logic driving a selection block and a switch block according to said phase information supplied by said phase comparator; and
wherein said control logic comprises a logic machine issuing selection signals and enable signals according to said phase information.
13. A circuit for recovering a clock signal from an input data signal in a telecommunications network, comprising:
a generating means configured to generate a recovery clock signal;
a phase comparator configured to compare said input data signal phase and said recovery clock signal phase for supplying a phase information, which controls said generating means of said recovery clock signal;
a selection means;
wherein said generating means comprises a delay line having a plurality of taps for generating a plurality of delayed signals;
wherein said selection means comprises a selection block for selecting a first recovery signal and a second recovery signal from said plurality of delayed signals, and further comprises a switch block for switching between said first recovery signal and said second recovery signal.
14. The circuit according to claim 13 , further comprising a control logic configured to drive said selection block and said switch block according to said phase information supplied by said phase comparator.
15. The circuit according to claim 14 , wherein said control logic comprises a filter for filtering the phase information.
16. The circuit according to claim 14 , wherein said control logic comprises a logic machine issuing selection signals and enable signals according to the phase information.