IP Library Granted Patent US 7,280,090
Granted Patent B2
US 7,280,090 · App. 09/748,623 · Granted Oct 9, 2007

Methods and apparatus for repairing inoperative pixels in a display

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Quick Facts
Patent No.
US 7,280,090
App. No.
09/748,623
Granted
Oct 9, 2007
Kind
B2
Abstract

Methods and apparatus for repairing inoperative pixels in a display are provided. In particular, the present invention provides methods and apparatus for improving the effective yield rates of displays, such as liquid crystal micro-displays, by disconnecting inoperative pixels from their defective drive circuitry and tying such pixels to the working drive circuit of a nearby pixel. A display can be repaired without the need to provide redundant drive circuitry underneath each pixel.

Claims (31)

1. A method for mitigating defects caused by inoperative pixels in a liquid crystal micro-display built on a silicon integrated circuit substrate, the substrate having an integral complimentary metal-oxide semiconductor (CMOS) control chip containing CMOS drive circuitry, the drive circuitry comprising a plurality of pixel drive circuits, each pixel drive circuit electrically connected to a corresponding pixel, the method comprising:

identifying a defective pixel drive circuit electrically connected to an inoperative pixel;

disconnecting the electrical connection between the defective pixel drive circuit and the inoperative pixel; and

electrically connecting the inoperative pixel to a working pixel drive circuit coupled to a nearby pixel such that the defective pixel drive circuit is bypassed and the inoperative pixel is driven from the working pixel drive circuit of the nearby pixel, the nearby pixel comprising one of an adjacent pixel or a non-adjacent pixel.

2. A method in accordance with claim 1 , wherein electrically connecting comprises using a bypass bit latch comprising a bypass bit, and wherein the bypass bit is loaded from an external memory after the display is turned on.

3. A method in accordance with claim 1 , further comprising: multiplexing the drive circuits of each pixel with the drive circuit of a nearby pixel.

4. A method in accordance with claim 1 , wherein electrically connecting comprises using a bypass bit latch comprising a bypass bit, and wherein the method further comprises:

providing a tn-state transistor associated with each pixel which is connected to the bypass bit latch; and

providing a resistor for coupling neighboring pixels;

such that when the bypass bit is set, the transistor is switched to bypass the defective pixel drive circuit so that the inoperative pixel is driven from the working pixel drive circuit of a nearby pixel through the resistor.

5. A method in accordance with claim 1 , wherein defects of the inoperative pixels are mitigated in groups.

6. A method in accordance with claim 1 , wherein identifying defective pixel drive circuit further comprises providing test circuitry associated with the display.

7. A method in accordance with claim 1 , wherein the pixel drive circuitry associated with each pixel is located separately from each pixel.

8. A liquid crystal micro-display apparatus capable of mitigating defects caused by inoperative pixels, comprising:

a plurality of pixels;

a complimentary metal-oxide semiconductor (CMOS) control chip integral to a silicon integrated circuit substrate of the micro display, the CMOS control chip comprising a plurality of pixel drive circuits, each pixel drive circuit electrically connected to a corresponding pixel,

means for disconnecting the electrical connection between the defective pixel drive circuit and an inoperative pixel; and

a means for electrically connecting the inoperative pixel to a working pixel drive circuit of a nearby pixel, such that the defective pixel drive circuit is bypassed and the inoperative pixel is driven from the working pixel drive circuit of the nearby pixel, the nearby pixel comprising one of an adjacent pixel or a non-adjacent pixel.

9. Apparatus in accordance with claim 8 , wherein the means for electrically connecting comprises a bypass bit latch comprising a bypass bit that is loaded from an external memory after the display is turned on.

10. Apparatus in accordance with claim 8 , further comprising: multiplexing circuitry associated with the connecting means.

11. Apparatus in accordance with claim 8 , wherein the means for electrically connecting comprises a bypass bit latch comprising a bypass bit, and wherein the apparatus further comprises:

a tri-state transistor associated with each pixel connected to the bypass bit latch; and

a resistor coupling neighboring pixels;

such that when the bypass bit is set, the transistor is switched to bypass the defective pixel drive circuit so that the inoperative pixel is driven from the working pixel drive circuit of a nearby pixel through the resistor.

12. Apparatus in accordance with claim 8 , wherein defects of the inoperative pixels are mitigated in groups.

13. Apparatus in accordance with claim 8 , further comprising test circuitry to identify the defective pixel drive circuit.

14. Apparatus in accordance with claim 8 , wherein the pixel drive circuitry associated with each pixel is located separately from each pixel.

15. A method in accordance with claim 1 , wherein the defective CMOS pixel drive circuit is identified after the CMOS control chip and the liquid crystal material are assembled together.

16. A method in accordance with claim 15 , wherein the inoperative pixel is identified via an optical inspection of the display after assembly of the display.

17. Apparatus in accordance with claim 8 , wherein the defective CMOS pixel drive circuit is identified after the CMOS control chip and the liquid crystal material are assembled together.

18. Apparatus in accordance with claim 17 , wherein the inoperative pixel is identified via an optical inspection of the display after assembly of the display.

Assignments (8)
ASSIGNMENT OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2025
From: ROYAL BANK OF CANADA [RESIGNING COLLATERAL AGENT]
To: GLAS USA LLC [SUCCESSOR COLLATERAL AGENT]
Reel/Frame 070097/0810 →
RELEASE OF PATENT SECURITY INTEREST Recorded Dec 3, 2024
From: CERBERUS BUSINESS FINANCE AGENCY, LLC
To: ELECTRONICS FOR IMAGING, INC.; FIERY, LLC
Reel/Frame 069477/0479 →
SECURITY INTEREST Recorded Mar 12, 2024
From: ELECTRONICS FOR IMAGING, INC.; FIERY, LLC
To: CERBERUS BUSINESS FINANCE AGENCY, LLC
Reel/Frame 066794/0315 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2024
From: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS AGENT
To: ELECTRONICS FOR IMAGING, INC.
Reel/Frame 066793/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 23, 2019
From: CITIBANK, N.A., AS ADMINISTRATIVE AGENT
To: ELECTRONICS FOR IMAGING, INC.
Reel/Frame 049840/0316 →
SECURITY INTEREST Recorded Jul 23, 2019
From: ELECTRONICS FOR IMAGING, INC.
To: ROYAL BANK OF CANADA
Reel/Frame 049840/0799 →
SECOND LIEN SECURITY INTEREST IN PATENT RIGHTS Recorded Jul 23, 2019
From: ELECTRONICS FOR IMAGING, INC.
To: DEUTSCHE BANK TRUST COMPANY AMERICAS
Reel/Frame 049841/0115 →
GRANT OF SECURITY INTEREST IN PATENTS Recorded Jan 3, 2019
From: ELECTRONICS FOR IMAGING, INC.
To: CITIBANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 048002/0135 →