CMOS sensor array with a memory interface
View Patent ↗An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.
1. An imaging system, comprising:
an image sensor, comprising:
a sensor array, including a two-dimensional array of pixel elements, that outputs digital signals as pixel data representing an image of a scene;
a data memory coupled to said sensor array and fabricated with said sensor array on a first integrated circuit, said data memory for storing said pixel data, wherein said data memory is configured using a first memory interface protocol;
a logic circuit coupled to said data memory and fabricated with said data memory on said first integrated circuit, said logic circuit for accessing said data memory using said first memory interface protocol and performing memory interface conversion to provide an output memory interface configured using a second memory interface protocol different than said first memory interface protocol for exporting said pixel data out of said first integrated circuit; and
an image processing device formed on a second integrated circuit separate from said first integrated circuit and including a memory interface port configured using said second memory interface protocol;
wherein said image sensor is coupled to said memory interface port of said image processing device and said image processing device accesses pixel data in said image sensor using said second memory interface protocol.
2. The imaging system of claim 1 , wherein said second memory interface protocol of said image sensor is a SRAM interface protocol.
3. The imaging system of claim 1 , wherein said second memory interface protocol of said image sensor is a DRAM interface protocol.
4. The imaging system of claim 1 , wherein said second memory interface protocol of said image sensor is a packet protocol synchronous DRAM interface protocol.