Interrupt controller in an interface device or information processing system
View Patent ↗There is disclosed an interface device which can prevent the freezing of an information processing system caused occupation of a system bus even when a wait signal outputted from the PC card is kept asserted. When the wait signal outputted from the PC card, is asserted, a timer portion 201 is activated. When the timer portion 201 detects that the wait signal is kept asserted for more than a predetermined period of time, it asserts a wait mask signal. Upon assertion of the wait mask signal, a mask portion 202 masks the wait signal from the PC card so that the wait signal to the CPU is negated even when the wait signal is kept asserted. Further, when the timer portion 201 asserts the wait mask signal, an interrupt control block/card status register 210 asserts an interrupt signal to the CPU.
1. An interface device for establishing an interface between a CPU and an external unit, comprising:
a timer portion,
a mask portion, and
an interrupt controlling portion, wherein:
said timer portion asserts a mask signal when detecting that a wait signal outputted from said external unit is kept asserted for more than a predetermined period of time,
said mask portion masks said wait signal and outputs it to said CPU when said mask signal is asserted; and
said interrupt controlling portion issues an interrupt signal to said CPU when said mask signal is asserted.
2. An information processing system comprising a CPU and an interface device for establishing an interface between said CPU and an external unit, wherein:
when said interface device detects that a wait signal outputted from said external unit has been kept asserted for more than a predetermined period of time, said interface device masks the wait signal for outputting to said CPU and issues an interrupt signal to said CPU to prevent freezing of the information processing system caused by occupation of a bus of the information processing system when said wait signal has been kept asserted.
3. An information processing system according to claim 2 , wherein said interface device includes a timer portion, a mask portion and an interrupt controlling portion, wherein
said timer portion is activated when the wait signal outputted from said external unit is asserted, and then asserts a mask signal when said wait signal is kept asserted for more than a predetermined period of time;
said mask portion masks said wait signal for outputting to said CPU when said mask signal is asserted; and
said interrupt controlling portion issues an interrupt signal to said CPU when said mask signal is asserted.
4. An information processing system according to claim 3 , wherein said CPU detects said interrupt signal thereby to recover said external unit.
5. An information processing system according to claim 2 , wherein said CPU detects said interrupt signal thereby to recover said external unit.