IP Library › Granted Patent US 6,681,193
Granted Patent Utility
US 6,681,193 · Confirmation No. 6527

METHOD FOR TESTING A CMOS INTEGRATED CIRCUIT

Inventor: Carlo Dallavalle
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2003-10-06 IFEE Issue Fee Payment (PTO-85B) 1 View
2003-10-06 FRPR Certified Copy of Foreign Priority Application 28 View
2001-01-18 TRNA Transmittal of New Application 1 View
2001-01-18 A.PE Preliminary Amendment 9 View
2001-01-18 SPEC Specification 9 View
2001-01-18 CLM Claims 3 View
2001-01-18 ABST Abstract 1 View
2001-01-18 DRW Drawings-only black and white line drawings 1 View
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Quick Facts
Patent No.
US 6,681,193
App. No.
09/765,502
Filed
2001-01-18
Granted
2004-01-20
Pub. No.
US20020029124A1
Examiner
LAU, TUNG S
Art Unit
2863
PTA
-113 days