IP Library Granted Patent US 6,844,237
Granted Patent B1
US 6,844,237 · App. 09/774,323 · Granted Jan 18, 2005

Method for improving dielectric polishing

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Quick Facts
Patent No.
US 6,844,237
App. No.
09/774,323
Granted
Jan 18, 2005
Kind
B1
Abstract

According to one embodiment, a shallow trench isolation (STI) method ( 500 ) may include forming an etch mask layer over both a first and second substrate side ( 504 ). An etch mask layer over a first substrate side ( 506 ) may be patterned to form a STI etch mask, and trenches may be etched into a substrate ( 508 ). A trench dielectric layer can be formed over a first substrate side ( 510 ). An etch mask layer formed over a second substrate side can be etched ( 512 ), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step 514 ).

Claims (45)

1. A method, comprising the steps of:

forming a first layer comprising deposited silicon nitride over a first and second side of a substrate:

maintaining the second side of the substrate essentially free of any other overlying layers;

removing at least a portion of the first layer formed over the second side of the substrate; and

forming device features on the first side of the substrate.

2. The method of claim 1 , wherein:

removing at least a portion of the first layer formed over the second side of the substrate includes wet chemically etching with phosphoric acid.

3. The method of claim 1 , wherein:

the layer of silicon nitride has a thickness of less than 3,000 Å.

4. The method of claim 1 , wherein:

removing at least a portion of the first layer formed over the second side of the substrate includes isotropically etching.

5. The method of claim 1 , wherein:

forming device features includes polishing a dielectric layer.

6. The method of claim 5 , wherein:

polishing the dielectric layer includes chemical-mechanical polishing a shallow trench dielectric layer.

7. The method of claim 1 , further including:

removing at least a portion of the first layer formed over the first side of the substrate.

8. The method of claim 7 , wherein:

removing at least a portion of the first layer formed over the first side of the substrate include forming a shallow trench isolation etch mask.

9. The method of claim 1 , further including:

forming a second layer over the first side of the substrate; and

removing at least a portion of the first layer formed over the second side of the substrate includes etching with a high degree of selectivity between the first layer and the second layer.

10. The method of claim 9 , where:

the second layer comprises silicon dioxide.

11. A method, comprising the steps of:

forming a first layer that includes a first part formed over a first substrate side and a second part formed over a second substrate side;

forming a second layer over the first part while maintaining the second substrate side essentially free of any other additional layers;

removing at least a portion of the second part; and

after removing at least the portion of the second part, forming features on the first substrate side.

12. The method of claim 11 , further including;

patterning the first part before forming the second layer.

13. The method of claim 11 , wherein:

removing at least a portion of the second part includes etching essentially all of the second part.

14. The method of claim 13 , further including:

the second layer serves as an etch mask to prevent etching of the first part.

15. A shallow trench isolation (STI) method, comprising the steps of:

forming a trench etch mask layer over a first and second substrate side, the trench etch mask layer including a layer of silicon nitride deposited over the first and second substrate sides;

maintaining the second substrate side essentially free of any additional overlying layers; and

removing at least a portion of the trench etch mask layer that is formed over the second substrate side.

16. The STI method of claim 15 , further including:

patterning the trench etch mask layer formed over the first substrate side and forming a trench dielectric over the first substrate side.

17. The STI method of claim 16 , further including:

etching a substrate to form trenches having a depth of less than 4,000 angstroms with the patterned trench etch mask layer as an etch mask.

18. The STI method of claim 16 , further including:

chemical-mechanical polishing the trench dielectric.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2021
From: MONTEREY RESEARCH LLC
To: SPEARHEAD IP LLC
Reel/Frame 055029/0317 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2002
From: JIN, BO; ZAGREBELNY, ANDREY; BUCHANAN, MATT
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 013046/0213 →