Dielectric layer for semiconductor device and method of manufacturing the same
A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.
1. A multi-layer structure for a semiconductor device, comprising:
a silicate interface layer; and
a high-k dielectric layer overlying the silicate interface layer, wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.
2. The multi-layer structure of claim 1 , wherein the silicate interface layer has a dielectric constant greater than that of silicon nitride.
3. The multi-layer structure of claim 1 , wherein the silicate interface layer is formed of a metal silicate material (M 1-x Si x O 2 ).
4. The multi-layer structure of claim 3 , wherein x is approximately 0.30-0.99.
5. The multi-layer structure of claim 3 , wherein the metal “M” is selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).
6. The multi-layer structure of claim 1 , wherein the silicate interface layer is formed by an ALD technique, a MOCVD technique or a reactive sputtering technique.
7. The multi-layer structure of claim 1 , wherein the silicate interface layer is formed to a thickness of approximately 5-10 angstroms.
8. The multi-layer structure of claim 1 , wherein the high-k dielectric layer is a metal oxide layer.
9. The multi-layer structure of claim 8 , wherein the metal oxide layer is an HfO 2 layer, a ZrO 2 layer, a Ta 2 O 3 layer, an Al 2 O 3 layer, a TiO 2 layer, an Y 2 O 3 layer, or a BST layer, a PZT layer, or combinations thereof.
10. The multi-layer structure of claim 8 , wherein the metal oxide layer is formed using an ALD technique, a MOCVD technique or a reactive sputtering technique.
11. The multi-layer structure of claim 8 , wherein the silicate interface layer is formed of a metal silicate material, and wherein the metal of the silicate interface layer is the same as the metal of the metal oxide layer.
12. The multi-layer structure of claim 1 , wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers.
13. The multi-layer structure of claim 12 , wherein the first layer is formed of HfO 2 , Ta 2 O 3 , Y 2 O 3 or ZrO 2 and the second layer is formed of Al 2 O 3 .
14. The multi-layer structure of claim 12 , wherein the first layer has a first fixed charge and the second layer has a second fixed charge opposite that of the first fixed charge.
15. The multi-layer structure of claim 12 , wherein the thickness of the second layer is approximately one half the thickness of the first layer.
16. The multi-layer structure of claim 15 , wherein the first layer is formed to a thickness of approximately 10 angstroms and the second layer is formed to a thickness of approximately 5 angstroms.
17. The multi-layer structure of claim 12 , wherein a total thickness of the second layer is not more than approximately one third of the total thickness of the high-k dielectric layer.
18. The multi-layer structure of claim 12 , wherein the upper most layer of the high-k dielectric layer is Al 2 O 3 .
19. A multi-layer structure for a semiconductor device, comprising:
a silicate interface layer having a dielectric constant greater than that of silicon nitride; and
a high-k dielectric layer overlying the silicate interface layer,
wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers, and wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.
20. The multi-layer structure of claim 19 , wherein the silicate interface layer is formed of a metal silicate material (M 1-x Si x O 2 ), the metal “M” being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).
21. The multi-layer structure of claim 19 , wherein the first layer is formed of HfO 2 , Ta 2 O 3 , Y 2 O 3 or ZrO 2 and the second layer is formed of Al 2 O 3 .
22. The multi-layer structure of claim 19 , wherein the thickness of the second layer is approximately one half the thickness of the first layer.
23. The multi-layer structure of claim 19 , wherein a total thickness of the second layer is not more than approximately one third of the total thickness of the high-k dielectric layer.
24. The multi-layer structure of claim 19 , wherein the upper most layer of the high-k dielectric layer is Al 2 O 3 .
25. A transistor comprising:
a substrate;
a silicate interface layer formed over the substrate; and
a high-k dielectric layer formed over the silicate interface layer;
a gate formed over the high-k dielectric layer; and
a source/drain region formed adjacent the gate, wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.
26. The transistor of claim 25 , wherein an upper most portion of the high-k dielectric layer is Al 2 O 3 , and wherein said gate comprises poly-silicon.
27. A non-volatile memory, comprising:
a substrate;
a floating gate overlying the substrate;
a silicate interface layer formed over the floating gate;
a high-k dielectric layer formed over the silicate interface layer; and
a control gate overlying the high-k dielectric layer, wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.
28. A capacitor for a semiconductor device, comprising;
a lower electrode;
a silicate interface layer formed over the lower electrode;
a high-k dielectric layer formed over the silicate interface layer; and
an upper electrode formed over the high-k dielectric layer wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.
29. The multi-layer structure of claim 1 , wherein the multi-layer is used for a capacitor between a lower electrode and an upper electrode.
30. The multi-layer structure of claim 13 , wherein the multi-layer is used for a capacitor between a lower electrode and an upper electrode.
31. The multi-layer structure of claim 19 , wherein the multi-layer is used for a capacitor between a lower electrode and an upper electrode.
32. The multi-layer structure of claim 21 , wherein the multi-layer is used for a capacitor between a lower electrode and an upper electrode.
33. The transistor of claim 25 , wherein the silicate interface layer is formed of a metal silicate material (M 1-x Si x O 2 ), the metal “M” being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).
34. The transistor of claim 25 , wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers, and wherein the first layer is formed of HfO 2 , Ta 2 O 3 , Y 2 O 3 or Zro 2 and the second layer is formed of Al 2 O 3 .
35. The non-volatile memory of claim 27 , wherein the silicate interface layer is formed of a metal silicate material (M 1-x Si x O 2 ), the metal “M” being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).
36. The non-volatile memory of claim 27 , wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers, and wherein the first layer is formed of HfO 2 , Ta 2 O 3 , Y 2 O 3 or Zro 2 and the second layer is formed of Al 2 O 3 .
37. The capacitor of claim 28 , wherein the silicate interface layer is formed of a metal silicate material (M 1-x Si x O 2 ), the metal “M” being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).
38. The capacitor of claim 28 , wherein the high-k
dielectric layer comprises one or more ordered pairs of first and second layers, and, wherein the first layer is formed of HfO 2 , Ta 2 O 3 , Y 2 O 3 or Zro 2 and the second layer is formed of Al 2 O 3 .
39. A capacitor, comprising:
a lower electrode;
a silicate interface layer having a dielectric constant greater than that of silicon nitride;
a high-k dielectric layer overlying the silicate interface layer,
wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers, and wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer; and
an upper electrode.
40. The capacitor of claim 39 , wherein the silicate interface layer is formed of a metal silicate material (M 1-x Si x O 2 ), the metal “M” being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).
41. The capacitor of claim 39 , wherein the first layer is formed of HfO 2 , Ta 2 O 3 , Y 2 O 3 or ZrO 2 and the second layer is formed of Al 2 O 3 .