Circuit and method for performing a two-dimensional transform during the processing of an image
View Patent ↗An image decoder performs a 2-D transform as a series of 1-D transforms, and does so in a more efficient manner than prior decoders. The decoder includes a memory and a processor coupled to the memory. The processor is operable to store a column of values in the memory as a row of values, combine the values within the stored row to generate a column of resulting values, and store the resulting values in the memory as a row of resulting values. Such an image decoder can store values in a memory register such that when the processor combines these values to generate intermediate IDCT values, it stores these intermediate IDCT values in a transposed fashion. Thus, such an image decoder reduces the image-processing time by combining the generating and transposing of the intermediate IDCT values into a single step. The image decoder can store the values in a memory register such that when the processor combines these values to generate the intermediate IDCT values, it stores these intermediate IDCT values in a transposed and even-odd-separated fashion. Thus, such an image decoder reduces the image-processing time by combining the generating, transposing, and even-odd separating of the intermediate IDCT values into a single step.
1. An image decoder, comprising:
a memory having rows of storage locations; and
a processor coupled to the memory and operable to,
store in a row of the memory intermediate values from first and second matrix columns,
combine the stored intermediate values within the row to generate resulting values for third and fourth matrix columns, and
store the resulting values in respective rows of the memory.
2. The image decoder of claim 1 wherein the intermediate values comprise Masaki values.
3. The image decoder of claim 1 , wherein:
the memory comprises first, second, and third rows of storage locations; and
the processor is operable to,
store the intermediate values in the first row of storage locations,
store a first of the resulting values in the second row of storage locations, and
store a second of the resulting values in the third row of storage locations.
4. The image decoder of claim 1 wherein the processor is operable to generate the intermediate values.
5. The image decoder of claim 1 wherein the resulting values comprise respective partial inverse-transform values.
6. An image decoder, comprising:
a memory;
a processor coupled to the memory and operable to,
store a column of intermediate values in the memory as a row of intermediate values,
combine the intermediate values within the stored row to generate a column of resulting values, and
store the resulting values in the memory as a row of resulting values;
wherein the intermediate values comprise an even-position even intermediate value, an odd-position even intermediate value, an even-position odd intermediate value, and an odd-position odd intermediate value;
wherein the row has storage locations; and
wherein the processor is operable to store,
the even-position even intermediate value and the even-position odd intermediate value in respective adjacent storage locations, and
the odd-position even intermediate value and odd-position odd intermediate value in respective adjacent storage locations.
7. An image decoder, comprising:
a memory;
a processor coupled to the memory and operable to,
store a column of intermediate values in the memory as a row of intermediate values,
combine the intermediate values within the stored row to generate a column of resulting values, and
store the resulting values in the memory as a row of resulting values;
wherein the intermediate values comprise an even-position even intermediate value, an odd-position even intermediate value, an even-position odd intermediate value, and an odd-position odd intermediate value;
wherein the row has storage locations; and
wherein the processor is operable to store,
the even-position even intermediate value and the even-position odd intermediate value in a first pair of adjacent storage locations, the second pair of storage locations being adjacent to the first pair of adjacent storage locations.
8. An image decoder, comprising:
a memory;
a processor coupled to the memory and operable to,
store a column of intermediate values in the memory as a row of intermediate values,
combine the intermediate values within the stored row to generate a column of resulting values, and
store the resulting values in the memory as a row of resulting values;
wherein the intermediate values comprise a first even-position even intermediate value, an odd-position even intermediate value, a second even-position even intermediate value, a first even-position odd intermediate value, an odd-position odd intermediate value, and a second even-position odd intermediate value;
wherein the row has storage locations; and
wherein the processor is operable to store,
the first even-position even intermediate value and the first even-position odd intermediate value in a first pair of adjacent storage locations,
the second even-position even intermediate value and the second even-position odd intermediate value in a second pair of adjacent storage locations, the second pair of storage locations being adjacent to the first pair of storage locations, and
the odd-position even intermediate value and the odd-position odd intermediate value in a third pair of adjacent storage locations.
9. An image decoder, comprising:
memory rows; and
a processor couple to the memory rows and operable to,
combine a first matrix column of first values with a second matrix column of second values to generate a portion of a resulting matrix column of resulting values; and
store the resulting values in more than one of the memory rows to convert the portion of the resulting matrix column into a corresponding portion of a resulting matrix row.
10. The image decoder of claim 9 wherein:
the first values comprise even Masaki values; and
the second values comprise odd Masaki values.
11. The image decoder of claim 9 wherein the processor is further operable to store the first and second values of the first and second matrix columns in more than one of the memory rows.
12. The image decoder of claim 9 wherein the processor is operable to combine the first matrix column of first values with the second column of second values by adding the first values to the second values.
13. The image decoder of claim 9 wherein the processor is operable to combine the first matrix column of first values with the second matrix column of second values by subtracting the first values from the second values.
14. The image decoder of claim 9 wherein the processor is operable to generate the first matrix column of first values and the second matrix column of second values.
15. The image decoder of claim 9 wherein the resulting values comprise inverse-discrete-cosine-transform values.
16. The image decoder of claim 9 wherein an arrangement of the resulting values within the resulting matrix row is different than an arrangement of the resulting values within the resulting matrix column.
17. The image decoder of claim 9 wherein an arrangement of the resulting values within the resulting matrix row is the same as an arrangement of the resulting values within the resulting matrix column.
18. The image decoder of claim 9 wherein each of the memory rows comprises a single respective register.
19. The image decoder of claim 9 wherein:
the portion of the resulting matrix column comprises the entire matrix column; and
the portion of the resulting matrix row comprises the entire matrix row.
20. An image decoder, comprising:
first and second memory registers having respective storage locations; and
a processor coupled to the registers and operable to,
store each of a set of first intermediate values in every other respective storage location of the first memory register, the set of the first intermediate values corresponding to a set of initial values,
store each of a set of second intermediate values in remaining storage locations of the first memory register, the set of second intermediate values corresponding to the set of initial values,
combine each first intermediate value with a second intermediate value that occupies a respective adjacent storage location to generate respective resulting values; and
store each of the resulting values in a respective storage location of the second memory register.
21. The image decoder of claim 20 wherein:
the first intermediate values comprise even Masaki values; and
the second intermediate values comprise odd Masaki values.
22. The image decoder of claim 20 wherein the set of initial values comprises a block of discrete-cosine-transform coefficients.
23. The image decoder of claim 20 wherein:
the set of first intermediate values corresponds to a first subset of the set of initial values; and
the set of second intermediate values corresponds to a second subset of the set of initial values.
24. The image decoder of claim 20 wherein:
the set of initial values comprises rows of discrete-cosine-transform coefficients;
each of the first intermediate values corresponds to the discrete-cosine-transform coefficients tat occupy even locations of a respective row; and
each of the second intermediate values corresponds to the discrete-cosine-transform coefficients that occupy odd locations of the respective row.
25. The image decoder of claim 15 wherein:
the set of initial values comprises rows of discrete-cosine-transform coefficients, each row having respective even and odd locations;
the processor is operable to generate each of the first intermediate values from the discrete-cosine-transform coefficients that occupy even locations of a respective row; and
the processor is operable to generate each of the second intermediate values from the discrete-cosine-transform coefficients that occupy odd locations of the respective row.
26. The image decoder of claim 20 wherein the processor is operable to combine each first intermediate value with a second intermediate value by adding each first intermediate value to the second intermediate value tat occupies the respective adjacent storage location.
27. The image decoder of claim 20 wherein the processor is operable to combine each first intermediate value with a second intermediate value by subtracting each first intermediate value from the second intermediate value that occupies the respective adjacent storage location.
28. The image decoder of claim 20 wherein the processor is operable to:
store each of the set of first intermediate values by storing first and second ones of the first intermediate values in first and third storage locations, respectively, of the first memory register;
store each of the set of second intermediate values by storing first and second ones of the second intermediate values in second and fourth storage locations, respectively, of the first memory register;
combine each first intermediate value with a second intermediate value by combining the first and second ones of the first intermediate values with the first and second ones, respectively, of the second intermediate values to generate respective first and second resulting values; and
store each of the resulting values by storing first and second resulting values in first and second locations, respectively, of the second memory register.
29. The image decoder of claim 20 wherein the processor is operable to:
store each of the set of first intermediate values by storing first and third ones of the first intermediate values in first and third storage locations, respectively, of the first memory register;
store each of the set of second intermediate values by storing first and third ones of the second intermediate values in second and fourth storage locations, respectively, of the first memory register;
combine each first intermediate value with a second intermediate value by combining the first and third ones of the first intermediate values with the first and third ones, respectively, of the second intermediate values to generate respective first and second resulting values; and
store each of the resulting values by storing first and second resulting values in first and second locations, respectively, of the second memory register.
30. A method comprising:
storing in a row of a memory intermediate values from first and second matrix columns;
generating resulting values for third and fourth matrix columns by combining the stored intermediate values within the row; and
storing the resulting values in respective rows of the memory.
31. The method of claim 30 wherein the intermediate values comprise Masaki values.
32. The method of claim 30 , further comprising generating the first and second matrix columns of intermediate values.
33. A method comprising:
storing a column of intermediate values as a row of intermediate values;
generating a column of resulting values by combining the intermediate values within the stored row;
storing the resulting values as a row of resulting values;
wherein the intermediate values include an even-position even intermediate value, and odd-position odd intermediate value; and
wherein the storing the column of intermediate value comprises,
storing the even-position even intermediate value and the even-position odd intermediate value in respective adjacent storage locations of a row, and
storing the odd-position even intermediate value and the odd-position odd intermediate value in other respective adjacent storage locations of the row.
34. A method comprising:
storing a column of intermediate values as a row of intermediate values;
generating a column of resulting values by combining the intermediate values within the stored row;
storing the resulting values as a row of resulting values;
wherein the intermediate values include an even-position odd intermediate value, and an odd-position even intermediate value, and even-position odd intermediate value, and an odd-position odd intermediate value; and
wherein the storing the column of intermediate values comprises:
storing the even-position even intermediate value and the even-position odd intermediate value in a second pair of adjacent storage locations, the second pair of storage locations being adjacent to the first pair of adjacent storage locations.
35. A method, comprising:
storing a column of intermediate values as a row of intermediate values;
generating a column of resulting values by combining the intermediate values within the stored row;
storing the resulting values as a row of resulting values
wherein the intermediate values include a first even-position even intermediate value, an odd-position even intermediate value, a second even-position even intermediate value, a first even-position odd intermediate value, and odd-position odd intermediate value, and a second even-position odd intermediate value; and
wherein the storing the column of intermediate values comprises,
storing the first even-position even intermediate value and the first even-position odd intermediate value in a first pair of adjacent storage locations,
storing the second even-position even intermediate value and the second even-position odd intermediate value in a second pair of adjacent storage locations, the second pair of storage locations being adjacent to the first pair of storage locations, and
storing the odd-position even intermediate value and the odd-position odd intermediate value in a third pair of adjacent storage locations.
36. A method, comprising:
combining a first matrix column of first values with a second matrix column of second values to generate a portion of a resulting matrix column of resulting values; and
storing the resulting values in more than one row of a memory to convert the portion of the resulting matrix into a corresponding portion of a resulting matrix row.
37. The method of claim 36 wherein:
the first values comprise even Masaki values; and
the second values comprise odd Masaki values.
38. The method of claim 36 , further comprising storing the first and second values of the first and second matrix columns in more than one row of the memory.
39. The method of claim 36 wherein the combining comprises adding the first values to the second values.
40. The method of claim 36 wherein the combining comprises subtracting the first values from the second values.
41. The method of claim 36 , further comprising:
generating the first matrix column of first values; and
generating the second matrix column of second values.
42. The method of claim 36 wherein the resulting values comprise inverse-discrete-cosine-transform values.
43. A method, comprising:
storing each of a set of first intermediate values in every other respective storage location of a first memory register, the set of first intermediate values corresponding to a set of initial values;
storing each of a set of second intermediate values in remaining storage locations of the first memory register, the set of second intermediate values corresponding to the set of initial values;
generating respective resulting values by combining each first intermediate value with a second intermediate value that occupies a respective adjacent storage location of the first memory register; and
storing each of the resulting values in a respective storage location of a second memory register.
44. The method of claim 43 wherein:
the first intermediate values comprise even Masaki values; and
the second intermediate values comprise odd Masaki values.
45. The method of claim 43 wherein the set of initial values comprises a block of discrete-cosine-transform coefficients.
46. The method of claim 43 wherein:
the set of first intermediate values corresponds to a first subset of the set of initial values; and
the set of second intermediate values corresponds to a second subset of the set of initial values.
47. The method of claim 43 wherein:
the set of initial values comprises rows of discrete-cosine-transform coefficients;
each of the first intermediate values corresponds to the discrete-cosine-transform coefficients that occupy even locations of a respective row; and
each of the second intermediate values corresponds to the discrete-cosine-transform coefficients that occupy odd locations of the respective row.
48. The method of claim 43 , further comprising:
wherein the set of initial values comprises rows of discrete-cosine-transform coefficients, each row having respective even and odd locations;
generating each of the first intermediate values from the discrete-cosine-transform coefficients that occupy even locations of a respective row; and
generating each of the second intermediate values from the discrete-cosine-transform coefficients that occupy odd locations of the respective row.
49. The method of claim 43 wherein the generating comprises adding each first intermediate value to the second intermediate value that occupies the respective adjacent storage location of the first memory register.
50. The method of claim 43 wherein the generating comprises subtracting each first intermediate value from the second intermediate value that occupies the respective adjacent storage location of the first memory register.
51. The method of claim 43 wherein:
the storing the first intermediate value comprises storing first and second ones of the first intermediate values in first and third storage locations, respectively, of the first memory register;
the storing the second intermediate values comprises storing first and second ones of the second intermediate values in second and fourth storage locations, respectively, of the first memory register;
the generating comprises combining the first and second ones of the first intermediate values with the first and second ones, respectively, of the second intermediate values to generate respective first and second resulting values; and
the storing the resulting values comprises storing the first and second resulting values in first and second locations, respectively, of the second memory register.
52. The method of claim 43 wherein:
the storing the first intermediate values comprises storing first and third ones of the first intermediate values in first and third storage locations, respectively, of the first memory register;
the storing the second intermediate values comprises first and third ones of the second intermediate values in second and fourth storage locations, respectively, of the first memory register;
the generating comprises combining the first and third ones of the first intermediate values with the first and third ones, respectively, of the second intermediate values to generate respective first and second resulting values; and
the storing the resulting values comprises storing the first and second resulting values in first and second locations, respectively, of the second memory register.