Granted Patent
Re-Issue
US RE38,059
· Confirmation No. 4551
SEMICONDUCTOR INTEGRATED LOGIC CIRCUIT DEVICE USING A PASS TRANSISTOR
Patented Case
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-02-15 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-02-15 | SPEC |
Specification | 11 | View | |
| 2001-02-15 | CLM |
Claims | 20 | View | |
| 2001-02-15 | ABST |
Abstract | 1 | View | |
| 2001-02-15 | DRW |
Drawings-only black and white line drawings | 23 | View | |
| 2001-02-15 | LET. |
Miscellaneous Incoming Letter | 1 | View | |
| 2001-02-15 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-02-15 | SPEC |
Specification | 11 | View | |
| 2001-02-15 | CLM |
Claims | 20 | View | |
| 2001-02-15 | ABST |
Abstract | 1 | View | |
| 2001-02-15 | DRW |
Drawings-only black and white line drawings | 23 | View | |
| 2001-02-15 | LET. |
Miscellaneous Incoming Letter | 1 | View |
Inventors
Kazuo Yano
Hino-shi, JAPAN
Yasuhiko Sasaki
Kokubunji-shi, JAPAN
Attorneys & Agents of Record
Classification
USPC
716/1
H10D84/01
H03K19/1735
H10D84/907
H10D89/10
Prosecution
- Examiner
- SIEK, VUTHE
- Art Unit
- 2825
- Customer No.
- 24956
- Docket No.
- HIT 2 830-2
- Confirmation No.
- 4551
Foreign Priority
05-278055
·
1993-11-08
·
JAPAN
Patent Term Adjustment
0days
from
HITACHI, LTD.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-03-25
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Quick Facts
- Patent No.
- US RE38,059
- App. No.
- 09/783,597
- Filed
- 2001-02-15
- Granted
- 2003-04-01
- Examiner
- SIEK, VUTHE
- Art Unit
- 2825
- PTA
- 0 days
External Links