Digital signal processor
View Patent ↗A digital signal processor comprises an arithmetic device 12 wherein a reservation processing register 26 , to which setting to which from the arithmetic device 11 is possible and which has a construction for storing an address and an execution mode as a task list 18 , and a clear circuit 27 for clearing the execution mode when the address in the reservation processing register 26 is copied to a program counter 21 , are newly added. Threreby, in the digital signal processor comprising two arithmetic devices, it is possible to remove the processing waiting time as well as to change the processing order at respective arithmetic devices.
1. A digital signal processor comprising:
a main arithmetic device operable to generate a task demand; and
an auxiliary arithmetic device operable to receive the task demand from said main arithmetic device and to perform a demanded task, which corresponds to the task demand,
wherein said auxiliary arithmetic device comprises a program memory area having a task list stored therein a reservation processing register and a clear circuit,
wherein said program memory area includes previously stored therein, a plurality of tasks that are to be processed by said auxiliary arithmetic device in a prescribed cycle, and an interrupt task which is to be executed in accordance with the task demand,
wherein said task list defines an order in which the plurality of tasks stored in said program memory area are to be processed by said auxiliary arithmetic device,
wherein said reservation processing register is operable to set the task demand from said main arithmetic device even when said auxiliary arithmetic device is processing the plurality of tasks,
wherein said clear circuit is operable to clear the task demand in said reservation processing register after the interrupt task corresponding to the task demand set in said reservation processing register is executed, and
wherein said auxiliary arithmetic device is operable to execute the interrupt task corresponding to the task demand from said main arithmetic device only once, after terminating processing of one of the plurality of tasks.
2. The digital signal processor as defined in claim 1 , wherein
said auxiliary arithmetic device has a priority judgment circuit operable to determine a priority for performing the processing of the demanded task, to execute the processing, and
said auxiliary arithmetic device is operable to perform the demanded task in accordance with the priorities of respective tasks determined by said priority judgment circuit.
3. The digital signal processor as defined in claim 1 , wherein
said auxiliary arithmetic device has an interruption signal generation circuit operable to generate an interruption signal interrupting processing which is under execution, and
when receiving the task demand from said main arithmetic device, said auxiliary arithmetic device interrupts the processing which is under execution and performs the demanded task.