Apparatus for use in a computer system
View Patent ↗Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus ( 3 ) having latency intolerant modules connected thereto, a secondary bus ( 4 ) having latency tolerant modules connected thereto, and a primary to secondary bus interface module ( 5 ) interconnecting the primary and secondary buses.
1. An integrated circuit for a computer system comprising:
a bus architecture;
a plurality of modules connected to the bus architecture; and
an arbitration unit for granting access to the bus in response to requests received from the modules, the granting of access being in the form of a dedicated packet issued from the arbitration unit, whereby only the module which has been granted access can use that particular dedicated packet to gain access to the bus;
characterised in that the arbitration unit is operable to issue empty packets during periods when the bus is idle, the empty packets being usable by a module to gain access to the bus without making a specific request to the arbitration unit for a dedicated packet,
wherein the bus is a pipelined packet switched bus that is open-ended.
2. The integrated circuit as claimed in claim 1 , wherein the first module to use the empty packet gains access to the bus.
3. The integrated circuit as claimed in claim 1 , wherein each module has means for converting a dedicated packet intended for itself into an empty packet.
4. The integrated circuit as claimed in claim 1 , wherein the arbitration unit is located at one end of the bus.
5. A computer system comprising the integrated circuit as claimed in claim 1 .
6. A graphics processing system comprising the integrated circuit as claimed in claim 1 .
7. A games console comprising the integrated circuit as claimed in claim 1 .
8. A method of granting bus access to a module in an integrated circuit for a computer system comprising a plurality of modules interconnected by the bus, and an arbitration unit for granting access to the bus by issuing dedicated packets in response to requests received from the modules, the method comprising:
issuing empty packets from the arbitration unit during periods when the bus is idle; and,
allowing any module to use the empty packet in order to gain access to the bus,
wherein the bus is a pipelined packet switched bus that is open-ended.