IP Library Granted Patent US 6,886,171
Granted Patent B2
US 6,886,171 · App. 09/789,051 · Granted Apr 26, 2005

Caching for I/O virtual address translation and validation using device drivers

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Quick Facts
Patent No.
US 6,886,171
App. No.
09/789,051
Granted
Apr 26, 2005
Kind
B2
Abstract

A method and apparatus for input/output virtual address translation and validation assigns a range of memory to a device driver for its exclusive use. The device driver invokes system functionality for receiving a logical address and outputting a physical address having a length greater than the logical address. Another feature of the invention is a computer system providing input/output virtual address translation and validation for at least one peripheral device. In one embodiment, the computer system includes a scatter-gather table, an input/output virtual address cache memory associated with at least one peripheral device, and at least one device driver. In a further embodiment, the input/output virtual address cache memory includes an address validation cache and an address translation cache.

Claims (30)

1. In a computer system that implements input/output virtual address translation and validation, a method for enabling input/output virtual address translation and validation compnsing the steps of:

(a) assigning a range of memory to a device driver for its exclusive use, the device driver associated with a peripheral device; and

(b) invoking, by the device driver an operating system function to enable the computer system to receive a logical address and output a physical address, the physical address having a length greater than the logical address,

wherein the function is not specific to the peripheral device, and

wherein the function is a hardware abstraction layer function.

2. The method of claim 1 further comprising the step of assigning, by the device driver, a bus slot number to the peripheral device.

3. The method of claim 1 further comprising the step of initializing the computer.

4. The method of claim 3 further comprising the step of disabling input/output virtual address translation.

5. The method of claim 3 further comprising the step of assigning a range of memory to at least one attached peripheral device.

6. The method of claim 5 wherein the assigning further comprises the step of assigning a range of memory that is not physically contiguous to any other range of memory.

7. The method of claim 3 further comprising the step of reading at least one parameter from memory.

8. The method of claim 7 further comprising the step of allocating memory for at least one scatter-gather table based on the at least one parameter.

9. The method of claim 8 wherein the allocation is only performed if the at least one parameter is at least one of a set of predetermined valid table sizes.

10. The method of claim 8 wherein the at least one parameter further comprises a default table size.

11. The method of claim 8 further comprising the step of allocating memory for at least one input/output virtual address cache register and at least one enable register, both associated with the peripheral device.

12. The method of claim 3 further comprising the step of checking for valid peripheral device to peripheral device bridges.

13. The method of claim 3 further comprising the step of logging errors.

14. The method of claim 1 wherein step (b) comprises the step:

(b-a) if this is the first time the device driver is invoking the functionality, then enabling input/output virtual address translation and verification.

15. The method of claim 1 further comprising the step of mapping an address range in response to a driver request.

16. The method of claim 1 further comprising the step of freeing an address range in response to a driver request.

17. The method of claim 1 further comprising the step of invoking, by the device driver, system functionality to change a scatter-gather table.

18. The method of claim 17 further comprising the step of entering an address-range mapping into the scatter-gather table.

19. The method of claim 18 further comprising the step of returning the mapping to the peripheral device to use for memory transactions.

20. The method of claim 19 further comprising determining that a transaction is complete.

21. The method of claim 19 further comprising invalidating an entry in the scatter-gather table.

22. The method of claim 19 further comprising clearing an entry in an input-output virtual address cache.

23. The method of claim 1 further comprising the step of invoking the system functionality by the device driver to disable the input/output virtual address translation and validation.

24. The method of claim 23 further comprising the step of invalidating the appropriate entries in memory when no devices are using input/output virtual address translation and verification.

25. The method of claim 23 further comprising decrementing a counter until no devices are using input/output virtual address translation.

Assignments (22)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057254/0557) Recorded Aug 29, 2022
From: CERBERUS BUSINESS FINANCE AGENCY, LLC
To: STRATUS TECHNOLOGIES IRELAND LIMITED; STRATUS TECHNOLOGIES BERMUDA LTD.
Reel/Frame 061354/0599 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Jun 9, 2021
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To: CERBERUS BUSINESS FINANCE AGENCY, LLC, AS COLLATERAL AGENT
Reel/Frame 057254/0557 →
SECURITY INTEREST Recorded Apr 3, 2020
From: STRATUS TECHNOLOGIES IRELAND LIMITED
To: TRUST BANK (AS SUCCESSOR BY MERGER TO SUNTRUST BANK)
Reel/Frame 052316/0371 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2020
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: STRATUS TECHNOLOGIES IRELAND LTD.
Reel/Frame 052210/0411 →
SECURITY INTEREST Recorded Apr 28, 2014
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: SUNTRUST BANK
Reel/Frame 032776/0595 →
RELEASE OF PATENT SECURITY AGREEMENT (SECOND LIEN) Recorded Apr 28, 2014
From: WILMINGTON TRUST NATIONAL ASSOCIATION; SUCCESSOR-IN-INTEREST TO WILMINGTON TRUST FSB AS SUCCESSOR-IN-INTEREST TO DEUTSCHE BANK TRUST COMPANY AMERICAS
To: STRATUS TECHNOLOGIES BERMUDA LTD.
Reel/Frame 032776/0536 →
RELEASE OF SUPER PRIORITY PATENT SECURITY AGREEMENT Recorded Apr 28, 2014
From: JEFFERIES FINANCE LLC
To: STRATUS TECHNOLOGIES BERMUDA LTD.
Reel/Frame 032776/0555 →
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Reel/Frame 032776/0579 →
INDENTURE PATENT SECURITY AGREEMENT Recorded Apr 9, 2010
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 024202/0766 →
SUPER PRIORITY PATENT SECURITY AGREEMENT Recorded Apr 9, 2010
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: JEFFERIES FINANCE LLC, AS ADMINISTRATIVE AGENT
Reel/Frame 024202/0736 →
RELEASE OF SECURITY INTEREST Recorded Apr 9, 2010
From: GOLDMAN SACHS CREDIT PARTNERS L.P.
To: STRATUS TECHNOLOGIES BERMUDA LTD.
Reel/Frame 024213/0375 →
RELEASE OF SECURITY INTEREST Recorded Apr 6, 2010
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RELEASE OF SECURITY INTEREST Recorded Apr 6, 2010
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Reel/Frame 024185/0931 →
PATENT SECURITY AGREEMENT (FIRST LIEN) Recorded Apr 3, 2006
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: GOLDMAN SACHS CREDIT PARTNERS L.P.
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PATENT SECURITY AGREEMENT (SECOND LIEN) Recorded Apr 3, 2006
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: DEUTSCHE BANK TRUST COMPANY AMERICAS
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RELEASE OF SECURITY INTEREST Recorded Mar 31, 2006
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SECURITY AGREEMENT Recorded May 28, 2002
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To: JPMORGAN CHASE BANK, AS ADMINISTRATIVE AGENT
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SECURITY AGREEMENT Recorded Dec 10, 2001
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