Graphic display system having a frame buffer with first and second memory portions
View Patent ↗A graphics display system has a graphics processor system for forming a color image on a display, the display being composed of an array of pixels. A memory system has a first memory for storing at least respective color data and respective Z data that is render from primitives of the image, and a second memory for storing respective display data, derived from the rendered color data and Z data, for each of the pixels. The graphics processor system has a memory interface operatively connected to the first and second memories. During formation of an image frame, the memory interface writes to and reads from a Z buffer, and only writes to a render target color buffer. After the image is rendered, image data is copied from the first memory to the second memory from which the image is displayed.
1. A graphics display system, comprising:
a graphics processor system for forming a color image on a display, the display being composed of an array of pixels;
a memory system having a first memory for storing at least respective color data and respective Z data rendered from primitives of the image, and a second memory for storing respective display data, which is formed from the color data and Z data, for each of the pixels;
wherein the first memory has a higher bandwidth than a bandwidth of the second memory;
the graphics processor system having a memory interface operatively connected to the first and second memories; and
wherein the first memory is a logic enhanced dynamic random access memory that includes at least render backend logic.
2. The system according to claim 1 , wherein the graphics processor, the first memory and the second memory are respectively integrated on three separate chips.
3. The system according to claim 1 , wherein the graphics processor, the first memory and the second memory are respectively integrated onto a common chip.
4. The system according to claim 1 , wherein the graphics processor and the first memory are integrated onto a first chip, and wherein the second memory is integrated onto a second chip.
5. The system according to claim 1 , wherein the graphics processor and the memory interface are integrated on a common chip.
6. The system according to claim 1 , wherein the first memory is a dynamic random access memory (DRAM).
7. The system according to claim 1 , wherein the second memory is a dynamic random access memory (DRAM).
8. The system according to claim 1 , wherein each of the first and second memories is a dynamic random access memory (DRAM).
9. The system according to claim 1 , wherein the first memory includes a render target color buffer for storing at least respective color data rendered from primitives of the image, after primitives are rendered to the target render color buffer and the Z buffer, image data in the first memory is copied to the second memory to form display data in the display color buffer in the second memory.
10. A graphics display system, comprising:
a graphics processor for forming a color image on a display, the display being composed of an array of pixels;
a logic enhanced DRAM memory for storing at least respective color data and respective Z data rendered from primitives of the image, and having at least render backend logic, the logic enhanced DRAM memory being a first memory;
a further DRAM memory for storing respective display data, which is formed from at least the color data and Z data, for each of the pixels, the further DRAM memory being a second memory;
wherein the first memory has a higher bandwidth than a bandwidth of the second memory; and
the graphics processor having a memory interface operatively connected to the logic enhanced DRAM memory and to the further DRAM memory.
11. The system according to claim 10 , wherein the graphics processor, the first memory and the second memory are respectively integrated on three separate chips.
12. The system according to claim 10 , wherein the graphics processor, the first memory and the second memory are respectively integrated onto a common chip.
13. The system according to claim 10 , wherein the graphics processor and the first memory are integrated onto a first chip, and wherein the second memory is integrated onto a second chip.
14. The system according to claim 10 , wherein the graphics processor and the memory interface are integrated on a common chip.
15. The system according to claim 10 , wherein, during formation of an image frame, the memory interface writes to and reads from the z buffer and the color buffer.
16. The system according to claim 10 , wherein the first memory includes a render target color buffer for storing at least respective color data rendered from primitives of the image, after primitives are rendered to the target render color buffer and the Z buffer, image data in the first memory is copied to the second memory to form display data in the display color buffer in the second memory.
17. A graphics display system, comprising:
a graphics processor system for forming a color image on a display, the display being composed of an array of pixels;
a memory system coupled to the graphics processor system, the memory system having a first memory, the first memory having a target render color buffer for storing at least respective color data rendered from primitives of the image, and a Z buffer for storing respective Z data rendered from primitives of the image, wherein the first memory has a higher bandwidth than a bandwidth of the second memory, and the memory system having a second memory having a display color buffer for storing respective display data, which is formed from the color data and Z data, for each of the pixels of the display; and
the graphics processor system having a memory interface operatively connected to the first and second memories; and
during formation of an image frame, the memory interface writes to and reads from the Z buffer, and only writes to the render target color buffer.
18. The system according to claim 17 , wherein the second memory is approximately three times larger than the first memory.
19. The system according to claim 17 , wherein the graphics processor, the first memory and the second memory are respectively integrated on three separate chips.
20. The system according to claim 17 , wherein the graphics processor, the first memory and the second memory are respectively integrated onto a common chip.
21. The system according to claim 17 , wherein the graphics processor and the first memory are integrated onto a first chip, and wherein the second memory is integrated onto a second chip.
22. The system according to claim 17 , wherein the graphics processor and the memory interface are integrated on a common chip.
23. The system according to claim 17 , wherein the first memory is a dynamic random access memory (DRAM).
24. The system according to claim 17 , wherein the first memory is a logic enhanced dynamic random access memory that includes at least render backend logic.
25. The system according to claim 17 , wherein the second memory is a dynamic random access memory (DRAM).
26. The system according to claim 17 , wherein each of the first and second memories is a dynamic random access memory (DRAM).
27. The system according to claim 17 , wherein, after primitives are rendered to the target render color buffer and the Z buffer, image data in the first memory is copied to the second memory to form display data in the display color buffer in the second memory.