Granted Patent
Utility
US 6,353,565
· Confirmation No. 7441
Semiconductor device, semiconductor memory device and test-mode entry method
Inventor:
Shigemasa Ito
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-02-22 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-02-22 | SPEC |
Specification | 14 | View | |
| 2001-02-22 | CLM |
Claims | 3 | View | |
| 2001-02-22 | ABST |
Abstract | 1 | View | |
| 2001-02-22 | DRW |
Drawings-only black and white line drawings | 4 | View | |
| 2001-02-22 | OATH |
Oath or Declaration filed | 3 | View | |
| 2001-02-22 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-02-22 | SPEC |
Specification | 14 | View | |
| 2001-02-22 | CLM |
Claims | 3 | View | |
| 2001-02-22 | ABST |
Abstract | 1 | View | |
| 2001-02-22 | DRW |
Drawings-only black and white line drawings | 4 | View | |
| 2001-02-22 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Shigemasa Ito
Kasugai-shi, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/201
G11C29/46
Prosecution
- Examiner
- HOANG, HUAN
- Art Unit
- 2818
- Docket No.
- 108075-00042
- Confirmation No.
- 7441
Foreign Priority
2000-049781
·
2000-02-25
·
JAPAN
Publication
- Pub. No.
- US20010017804A1
- Pub. Date
- 2001-08-30
Patent Term Adjustment
-59days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-04-27
CHANGE OF NAME
Recorded 2010-07-22
from
FUJITSU LIMITED
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2008-12-12
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Quick Facts
- Patent No.
- US 6,353,565
- App. No.
- 09/789,727
- Filed
- 2001-02-22
- Granted
- 2002-03-05
- Pub. No.
- US20010017804A1
- Examiner
- HOANG, HUAN
- Art Unit
- 2818
- PTA
- -59 days
External Links