Packet-switched spread-spectrum system

1. A packet-switched system for communicating data, comprising:

a plurality of packet transmitters, each packet transmitter including,

a transmitter-first-in-first-out (transmitter-FIFO) memory, coupled to a data input, for storing data;

a demultiplexer, coupled to said transmitter-FIFO memory and having a plurality of outputs, for demultiplexing the stored data into a plurality of sub-data-sequence signals, with a respective sub-data-sequence signal at a respective output of said demultiplexer;

chip-sequence means for outputting a plurality of chip-sequence signals, with each chip-sequence signal orthogonal to the other chip-sequence signals in said plurality of chip-sequence signals;

a plurality of product devices, coupled to the plurality of outputs of said demultiplexer, respectively, and to said chip-sequence means, for multiplying each of the sub-data-sequence signals by a respective chip-sequence signal, thereby generating a plurality of spread-spectrum channels;

a combiner, coupled to the plurality of product devices, for algebraically combining the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

a header device, coupled to said combiner, for concatenating a header to the multichannel-spread-spectrum signal, thereby generating a packet-spread-spectrum signal in the form of a time series of signals comprising the header and the multichannel-spread-spectrum signal; and

a transmitter subsystem, coupled to said header device, for transmitting on a carrier frequency the packet-spread-spectrum signal using radio waves over a communications channel; and

a plurality of packet receivers, each packet receiver including,

a header processing device for processing a header in a received spread-spectrum signal in accord with a common chip sequence signal, to generate a control or timing signal;

receiver-spread-spectrum means for despreading a multichannel-spread-spectrum signal embedded in the spread-spectrum signal as a plurality of received spread-spectrum channels, respectively; and

a multiplexer coupled to said receiver-spread-spectrum means, for multiplexing the plurality of received spread-spectrum channels as received data.

2. The packet-switched system as set forth in claim 1 , with said chip-sequence means including a chip-sequence generator for generating the plurality of chip-sequence signals.

3. The packet-switched system as set forth in claim 1 , with said chip-sequence means including a memory for storing the plurality of chip-sequence signals.

4. A packet-switched system for communicating data, comprising:

a plurality of packet transmitters, each packet transmitter including,

a demultiplexer having a plurality of outputs, for demultiplexing input data into a plurality of sub-data-sequence signals, with a respective sub-data-sequence signal at a respective output of said demultiplexer;

spread-spectrum means, coupled to the plurality of outputs of said demultiplexer, for spread-spectrum processing each of the sub-data-sequence signals by a respective chip-sequence signal, thereby generating a plurality of spread-spectrum channels, with the respective chip-sequence signal different from each chip-sequence signal in a plurality of chip-sequence signals for spread-spectrum processing the plurality of sub-data sequence signals, respectively, and with the plurality of chip-sequence signals commonly used by the plurality of packet transmitters;

a combiner, coupled to the spread-spectrum means, for combining the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

header means, coupled to said combiner, for adding a header, to the multichannel-spread-spectrum signal, thereby generating a packet-spread-spectrum signal in the form of a time series of signals comprising the header and the multichannel-spread-spectrum signal; and

transmitter means, coupled to said header means, for transmitting at a carrier frequency the packet-spread-spectrum signal using radio waves over a communications channel; and

a plurality of packet receivers, each packet receiver including,

a header processing device for processing a header in a received spread-spectrum signal in accord with a common chip sequence signal, to generate a control or timing signal;

receiver-spread-spectrum means for despreading a multichannel-spread-spectrum signal embedded in the spread-spectrum signal as a plurality of received spread-spectrum channels respectively; and

a multiplexer, coupled to said receiver-spread-spectrum means, for multiplexing the plurality of received spread-spectrum channels as received data.

5. The packet-switched system as set forth in claim 4 , with said spread-spectrum means including:

generating means for generating the plurality of chip-sequence signals; and

a plurality of EXCLUSIVE-OR gates coupled between said demultiplexer, said combiner and said generating means, for multiplying the plurality of sub-data-sequence signals by the plurality of chip-sequence signals, respectively, thereby generating the plurality of spread-spectrum channels.

6. The packet-switched system as set forth in claim 4 , with said spread-spectrum means including a memory for storing the plurality of chip-sequence signals.

7. The packet-switched system as set forth in claim 4 , with said spread-spectrum means including a plurality of product devices for multiplying each of the sub-data-sequence signals by a respective chip-sequence signal of the plurality of chip sequence signals.

8. The packet-switched system as set forth in claim 4 , with said spread-spectrum means including a plurality of surface-acoustic-wave devices, with each surface-acoustic-wave device having an impulse response matched to a chip-sequence signal of the plurality of chip-sequence signals, respectively.

9. The packet-switched system as set forth in claim 4 , with said receiver-spread-spectrum means including a plurality of data-matched filters, with each data-matched filter having an impulse response matched to a chip-sequence signal of the plurality of chip-sequence signals, respectively.

10. The packet-switched system as set forth in claim 4 with said receiver-spread-spectrum means including a plurality of surface-acoustic-wave devices, with each surface-acoustic wave device having an impulse response matched to a chip-sequence signal of the plurality of chip-sequence signals, respectively.

11. The packet-switched system as set forth in claim 4 with said header processing device including a header-matched filter having an impulse response matched to the header.

12. A method, using a packet transmitter and a packet receiver, comprising the steps of:

demultiplexing, at the packet transmitter, data from a data input into a plurality of sub-data-sequence channels;

spread-spectrum processing, at the packet transmitter, the plurality of sub-data-sequence signals by a plurality of chip-sequence signals, respectively, thereby generating a plurality of spread-spectrum channels, with each of the plurality of chip-sequence signals different from other chip-sequence signals in the plurality of chip-sequence signals;

combining, at the packet transmitter, the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

concatenating, at the packet transmitter, a header to the multichannel-spread-spectrum signal, thereby generating a time series of signals comprising the header and the multichannel-spread-spectrum signal to form a packet-spread-spectrum signal;

transmitting, from the packet transmitter, on a carrier frequency using radio waves, the packet-spread-spectrum signal over a communications channel;

processing, at the packet receiver, the header in the packet-spread-spectrum signal, to generate a control or timing signal;

despreading, at the packet receiver the multichannel-spread-spectrum signal embedded in the packet-spread-spectrum signal as a plurality of received spread-spectrum channels, respectively; and

multiplexing, at the packet receiver, the plurality of received spread-spectrum channels as received data.

13. The method as set forth in claim 12 , further including encoding the input data as encoded data, with the step of demultiplexing including the step of demultiplexing the encoded data into the plurality of sub-data-sequence channels.

14. The method as set forth in claim 12 , further including scrambling the input data as encoded data, with the step of demultiplexing including the step of demultiplexing the encoded data into the plurality of sub-data sequence channels.

15. The method as set forth in claim 12 , further including encrypting the input data as encoded data, with the step of demultiplexing including the step of demultiplexing the encoded data into the plurality of sub-data-sequence channels.

16. The method as set forth in claim 12 , with the step of spread-spectrum processing including the step of multiplying the plurality of sub-data-sequence signals by the plurality of chip-sequence signals, respectively, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals different from other chip-sequence signals in the plurality of chip-sequence signals.

17. The method as set forth in claim 12 , with the step of spread-spectrum processing including the step of multiplying the plurality of sub-data-sequence signals by the plurality of chip-sequence signals, respectively, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip-sequence signals in the plurality of chip-sequence signals.

18. The method as set forth in claim 12 , 16 or 17 , with the step of combining including the step of algebraically combining the plurality of spread-spectrum channels as the multichannel-spread-spectrum signal.

19. The method as set forth in claim 12 , 16 , or 17 with the step of concatenating including the step of concatenating the header to the multichannel-spread-spectrum signal at an initial point of the multichannel-spread-spectrum signal, thereby generating the time series of signals.

20. The method as set forth in claim 12 , 16 , or 17 , with the step of concatenating including the step of concatenating the header to the multichannel-spread-spectrum signal, with the header followed in time by the multichannel-spread-spectrum signal, thereby generating the time series of signals.

21. The method as set forth in claim 12 , 16 or 17 , with the step of spread-spectrum processing including the step of outputting a respective chip-sequence signal of the plurality of chip-sequence signals in response to a respective sub-data-sequence signal of the plurality of sub-data-sequence signals, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip-sequence signals in the plurality of chip-sequence signals.

22. The method as set forth in claim 12 , 16 or 17 , with the step of spread-spectrum processing including the step of outputting a respective chip-sequence signal of the plurality of chip-sequence signals in response to a respective data symbol in a sub-data-sequence signal of the plurality of sub-data-sequence signals, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip sequence signals in the plurality of chip-sequence signals.

23. The method as set forth in claim 12 , wherein the step of processing the header comprises:

detecting the header in the packet-spread-spectrum signal;

outputting, responsive to detecting the header, a header-detection signal; and

generating, responsive to the header-detection signal, the control or timing signal.

24. The method as set forth in claim 12 or 23 , further including, after the step of multiplexing, the step of storing the received data.

25. The method as set forth in claim 12 or 23 , further including, after the step of multiplexing, the step of decoding the received data.

26. The method as set forth in claim 12 , further including, before the step of processing the header, translating the packet-spread-spectrum signal from a carrier frequency to a processing frequency.

27. A packet transmitter and a packet receiver, comprising:

transmitter-memory means for storing, at said packet transmitter, data from a data input, as stored data;

demultiplexing means, coupled to said transmitter-memory means, for demultiplexing, at said packet transmitter, the stored data into a plurality of sub-data-sequence channels;

spread-spectrum means, coupled to said demultiplexing means, for spread-spectrum processing, at said packet transmitter, the plurality of sub-data-sequence signals by a plurality of chip-sequence signals, respectively, thereby generating a plurality of spread-spectrum channels, with each of the plurality of chip-sequence signals different from other chip-sequence signals in the plurality of chip-sequence signals;

combiner means, coupled to said spread-spectrum means, for combining, at said packet transmitter, the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

header means, coupled to said combiner means, for concatenating, at said packet transmitter, a header to the multichannel-spread-spectrum signal, thereby generating a packet-spread-spectrum signal in the form of a time series of signals comprising the header and the multichannel-spread-spectrum signal;

transmitter means for transmitting, from said packet transmitter, on a carrier using radio waves, the packet-spread-spectrum signal over a communications channel;

means, coupled to the communications channel, for processing the header in the packet-spread-spectrum signal, to generate a timing or control signal;

receiver-spread-spectrum means, coupled to the communications channel, for despreading, at said packet receiver, the multichannel-spread-spectrum signal embedded in the packet-spread-spectrum signal as a plurality of received spread-spectrum channels, respectively; and

multiplexing means, coupled to said receiver-spread-spectrum means, for multiplexing, at said packet receiver, the plurality of received spread-spectrum channels as received data.

28. The packet transmitter and the packet receiver as set forth in claim 27 , further including, between said transmitter memory means and said demultiplexing means, encoding means for encoding the stored data as encoded data, with said demultiplexing means including means for demultiplexing the encoded data into the plurality of sub-data-sequence channels.

29. The packet transmitter and the packet receiver as set forth in claim 27 , further including, between said transmitter memory means and said demultiplexing means, encoding means for scrambling the stored data as encoded data, with said demultiplexing means including means for demultiplexing the encoded data into the plurality of sub-data-sequence channels.

30. The packet transmitter and the packet receiver as set forth in claim 27 , further including, between said transmitter memory means and said demultiplexing means, encoding means for encrypting the stored data as encoded data, with said demultiplexing means including means for demultiplexing the encoded data into the plurality of sub-data-sequence channels.

31. The packet transmitter and the packet receiver as set forth in claim 27 , with said spread-spectrum means including multiplying means for multiplying the plurality of sub-data-sequence signals by the plurality of chip-sequence signals, respectively, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals different from other chip-sequence signals in the plurality of chip-sequence signals.

32. The packet transmitter and the packet receiver as set forth in claim 27 , with said spread-spectrum means including multiplying means for multiplying the plurality of sub-data-sequence signals by the plurality of chip-sequence signals, respectively, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip-sequence signals in the plurality of chip-sequence signals.

33. The packet transmitter and the packet receiver as set forth in claim 27 , 31 or 32 , with said combiner means including means for algebraically combining the plurality of spread-spectrum channels as the multichannel-spread-spectrum signal.

34. The packet transmitter and the packet receiver as set forth in claim 27 , 31 or 32 , with said header means including means for concatenating the header to the multichannel-spread-spectrum signal at an initial point of the multichannel-spread-spectrum signal, thereby generating the time series of signals.

35. The packet transmitter and the packet receiver as set forth in claim 27 , 31 or 32 , with said header means including means for concatenating the header to the multichannel-spread-spectrum signal, with the header followed in time by the multichannel-spread-spectrum signal, thereby generating the time series of signals.

36. The packet transmitter and the packet receiver as set forth in claim 27 , with the said spread-spectrum means including spread-spectrum-memory means for outputting a respective chip-sequence signal of the plurality of chip-sequence signals in response to a respective sub-data-sequence signal of the plurality of sub-data-sequence signals, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip-sequence signals in the plurality of chip-sequence signals.

37. The packet transmitter and the packet receiver as set forth in claim 27 , with said spread-spectrum means including spread-spectrum-memory means for outputting a respective chip-sequence signal of the plurality of chip-sequence signals in response to a respective data symbol in a sub-data-sequence signal of the plurality of sub-data-sequence signals, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip-sequence signals in the plurality of chip-sequence signals.

38. The packet transmitter and the packet receiver as set forth in claim 27 , with said means for processing the header including means for detecting the header in the packet-spread-spectrum signal, for outputting, responsive to detecting the header, a header-detection signal, and for generating, from the header-detection signal, the control or timing signal.

39. The packet transmitter and the packet receiver as set forth in claim 27 , 36 or 37 , further including, after said multiplexing means, receiver-memory means for storing the received data.

40. The packet transmitter and the packet receiver as set forth in claim 27 , 36 or 37 , further including, after said multiplexing means, decoding means for decoding the received data.

41. The packet transmitter and the packet receiver as set forth in claim 27 , further including translating means for shifting the packet-spread-spectrum signal from the carrier frequency to a processing frequency.

42. The packet transmitter and the packet receiver as set forth in claim 27 , with said spread-spectrum means including spread-spectrum-memory means for outputting a respective chip-sequence signal of the plurality of chip-sequence signals in response to a respective data symbol in a sub-data-sequence signal of the plurality of sub-data-sequence signals, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of the chip-sequence signals different from other chip-sequence signals in the plurality of chip-sequence signals.

43. The packet transmitter and the packet receiver as set forth in claim 42 , further including, after said multiplexing means, decoding means for decoding the received data.

44. A packet transmitter and a packet receiver, comprising:

a demultiplexer, at the packet transmitter, for demultiplexing input data into a plurality of sub-data-sequence channels;

spread-spectrum means, coupled to the demultiplexer, for spread-spectrum processing, at the packet transmitter, the plurality of sub-data-sequence signals by a plurality of chip-sequence signals, respectively, thereby generating a plurality of spread-spectrum channels, with each of the plurality of chip-sequence signals different from other chip-sequence signals in the plurality of chip-sequence signals;

a combiner, coupled to the spread-spectrum means, for combining, at the packet transmitter, the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

a header device, coupled to the combiner, for concatenating, at the packet transmitter, a header to the multichannel-spread-spectrum signal, thereby generating a time series of signals comprising the header and the multichannel-spread-spectrum signal to form a packet-spread-spectrum signal;

a transmitter subsystem, coupled to the header device, for transmitting, from the packet transmitter, on a carrier frequency using radio waves, the packet-spread-spectrum signal over a communications channel;

a header processing device, coupled to the communications channel, for processing the header in the packet-spread-spectrum signal to generate a control or timing signal;

receiver-spread-spectrum means, coupled to the communications channel, for despreading, at the packet receiver, the multichannel-spread-spectrum signal embedded in the packet-spread-spectrum signal as a plurality of received spread-spectrum channels, respectively; and

a multiplexer, coupled to the receiver-spread-spectrum means, for multiplexing, at the packet receiver, the plurality of received spread-spectrum channels as received data.

45. The packet transmitter and the packet receiver as set forth in claim 44 , further including an encoder for encoding the input data as encoded data, with the demultiplexer including means for demultiplexing the encoded data into the plurality of sub-data-sequence channels.

46. The packet transmitter and the packet receiver as set forth in claim 44 , further including an encoder for scrambling the input data as encoded data, with the demultiplexer including means for demultiplexing the encoded data into the plurality of sub-data-sequence channels.

47. The packet transmitter and the packet receiver as set forth in claim 44 , further including an encoder for encrypting the stored data as encoded data, with the demultiplexer including means for demultiplexing the encoded data into the plurality of sub-data-sequence channels.

48. The packet transmitter and the packet receiver as set forth in claim 44 with the spread-spectrum means including a plurality of product devices for multiplying the plurality of sub-data-sequence signals by the plurality of chip-sequence signals, respectively, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals different from other chip-sequence signals in the plurality of chip-sequence signals.

49. The packet transmitter and the packet receiver as set forth in claim 44 , with the spread-spectrum means including a plurality of product devices for multiplying the plurality of sub-data-sequence signals by the plurality of chip-sequence signals, respectively, thereby generating the plurality of spread-spectrum, channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip-sequence signals in the plurality of chip-sequence signals.

50. The packet transmitter and the packet receiver as set forth in claim 44 , 48 or 49 , with the combiner including means for algebraically combining the plurality of spread-spectrum channels as the multichannel-spread-spectrum signal.

51. The packet transmitter and the packet receiver as set forth in claim 44 , 48 , or 49 , with the header device including means for concatenating the header to the multichannel-spread-spectrum signal at an initial point of the multichannel-spread-spectrum signal, thereby generating the time series of signals.

52. The packet transmitter and the packet receiver as set forth in claim 44 , 48 , or 49 , with the header device including means for concatenating the header to the multichannel-spread-spectrum signal, with the header followed in time by the multichannel-spread-spectrum signal, thereby generating the time series of signals.

53. The packet transmitter and packet receiver as set forth in claim 44 , 48 or 49 , with the spread-spectrum means including a memory for outputting a respective chip-sequence signal of the plurality of chip-sequence signals in response to a respective sub-data-sequence signal of the plurality of sub-data-sequence signals, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip-sequence signals in the plurality of chip-sequence signals.

54. The packet transmitter and packet receiver as set forth in claim 44 , 48 or 49 , with the spread-spectrum means including a memory for outputting a respective chip-sequence signal of the plurality of chip-sequence signals in response to a respective data symbol in a sub-data-sequence signal of the plurality of sub-data-sequence signals, thereby generating the plurality of spread-spectrum channels, with each chip-sequence signal in the plurality of chip-sequence signals orthogonal with respect to other chip-sequence signals in the plurality of chip-sequence signals.

55. The packet transmitter and the packet receiver as set forth in claim 44 , with the header processing device including means for detecting, at the processing frequency, the header in the packet-spread-spectrum signal, for outputting, responsive to detecting the header, a header-detection signal, and generating, from the header-detection signal, the control or timing signal.

56. The packet transmitter and the packet receiver as set forth in claim 44 or 48 , further including a receiver memory, coupled to the multiplexer, for storing the received data.

57. The packet transmitter and the packet receiver as set forth in claim 44 or 55 , further including a decoder, coupled to the multiplexer, for decoding the received data.

58. The packet transmitter and the packet receiver as set forth in claim 44 , further including a translating device for translating the packet-spread-spectrum signal from the carrier frequency to a processing frequency.

59. A transceiver comprising a packet transmitter and a packet receiver, the packet transmitter comprising:

(a) a demultiplexer for demultiplexing, input data into a plurality of sub-data-sequence channels;

(b) spread-spectrum means, coupled to the demultiplexer, for spread-spectrum processing the plurality of sub-data-sequence signals by a plurality of chip-sequence signals, respectively, thereby generating a plurality of spread-spectrum channels, with each of the plurality of chip-sequence signals different from other chip-sequence signals in the plurality of chip-sequence signals;

(c) a combiner for combining the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

(d) a header device for adding a header to the multichannel-spread-spectrum signal, thereby generating a time series of signals comprising the header and the multichannel-spread-spectrum signal to form a packet-spread-spectrum signal;

(e) a transmitter for transmitting the packet-spread-spectrum signal using radio waves; the packet receiver comprising:

(i) a header processing device, coupled to a communications channel, for processing a header in a received packet-spread-spectrum signal to generate a control or timing signal;

(ii) receiver-spread-spectrum means, coupled to the communications channel, for despreading, a multichannel-spread-spectrum signal embedded in the received packet-spread-spectrum signal as a plurality of received spread-spectrum channels, respectively; and

(iii) a multiplexer for multiplexing the plurality of received spread-spectrum channels as received data.