Granted Patent
Utility
US 6,566,720
· Confirmation No. 1875
BASE CELL LAYOUT PERMITTING RAPID LAYOUT WITH MINIMUM CLOCK LINE CAPACITANCE ON CMOS STANDARD-CELL AND GATE-ARRAY INTEGRATED CIRCUITS
Inventor:
Lawrence L. Aldrich
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-06-06 | DRW |
Drawings-only black and white line drawings | 9 | View | |
| 2001-02-27 | TRNA |
Transmittal of New Application | 3 | View | |
| 2001-02-27 | SPEC |
Specification | 15 | View | |
| 2001-02-27 | CLM |
Claims | 7 | View | |
| 2001-02-27 | ABST |
Abstract | 1 | View | |
| 2001-02-27 | DRW |
Drawings-only black and white line drawings | 7 | View | |
| 2001-02-27 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Lawrence L. Aldrich
Colorado Springs, CO
Attorneys & Agents of Record
Classification
USPC
257/369
Prosecution
- Examiner
- PRENTY, MARK V
- Art Unit
- 2822
- Docket No.
- UMI-315
- Confirmation No.
- 1875
Publication
- Pub. No.
- US20020040985A1
- Pub. Date
- 2002-04-11
Patent Term Adjustment
-97days
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE INCORRECTLY CITED PATENT NUMBER 6,566,720 FROM THE CHANGE OF NAME RECORDS PREVIOUSLY RECORDED ON REEL 026423 FRAME 0286. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
Recorded 2014-04-10
from
ALDRICH, LAWRENCE L.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-02-27
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Quick Facts
- Patent No.
- US 6,566,720
- App. No.
- 09/794,367
- Filed
- 2001-02-27
- Granted
- 2003-05-20
- Pub. No.
- US20020040985A1
- Examiner
- PRENTY, MARK V
- Art Unit
- 2822
- PTA
- -97 days
External Links