High-speed data processing using internal processor memory space
View Patent ↗Significant performance improvements can be realized in data processing systems by confining the operation of a processor within its internal register file so as to reduce the instruction count executed by the processor. Data, which is sufficiently small enough to fit within the internal register file, can be transferred into the internal register file, and execution results can be removed therefrom, using direct memory accesses that are independent of the processor, thus enabling the processor to avoid execution of load and store instructions to manipulate externally stored data. Further, the data and execution results of the processing activity are also accessed and manipulated by the processor entirely within the internal register file. The reduction in instruction count, coupled with the standardization of multiple processors and their instruction sets, enables the realization of a highly scaleable, high-performing symmetrical multi-processing system at manageable complexity and cost levels.
1. A method of processing a packet, the method comprising the steps of:
receiving the packet;
splitting the packet into a packet header portion and a packet body portion;
transferring, by an ingress element, the packet header portion to a register file space of a processor without executing an instruction by the processor to load the packet header portion;
processing the packet header using only instructions stored locally to the processor without invoking at least one of a load instruction and a store instruction by the processor; and
integrating, by an egress element, the processed packet header with the packet body in an output buffer.
2. The method of claim 1 , wherein the transferring step is performed without invoking at least one of a load instruction and a store instruction.
3. The method of claim 1 further comprising the step of:
transferring the packet header to the register file using a direct register access; and
transferring the packet body to the output buffer.
4. The method of claim 3 further comprising the steps of:
selecting an output port for transmission of the packet;
forwarding the integrated packet from the output buffer to the selected output port for transmission therefrom.
5. The method of claim 1 further comprising the steps of:
providing a plurality of identical processors executing a common instruction set, each processor storing the instruction set locally to the processor;
selecting a processor from among the plurality to process the packet header; and
causing the selected processor to process the packet header.
6. The method of claim 5 , wherein the step of selecting the processor is performed by a state machine responsive to the receipt of the packet at an input port.
7. The method of claim 5 , wherein the step of causing the selected processor to process the packet header is performed by at least one state machine configured to write the packet header to at least one fixed location in the register file accessible to the selected processor.
8. The method of claim 5 , further comprising the step of downloading a common instruction set to an instruction memory in each of the plurality of processors.
9. A packet-processing system for processing a packet received over a communications network, the system comprising:
an input port configured to receive the packet over the communications network and splitting the packet into a packet header portion and a packet body portion;
a processor associated with the input port;
a register file internal to the processor; and
an ingress element coupled to the input port, processor, and register file, the ingress element being configured to selecting the processor from among a plurality of processors to process the packet header based on availability of the processor, transfer at least one portion of the packet to the register file by invoking a Direct Register Access (DRA) command, wherein the processor processes the at least one portion of the packet in the register file in response to the DRA command and without invoking at least one of a load instruction and a store instruction.
10. The packet-processing system of claim 9 , wherein the ingress element is configured to select the processor from a plurality of candidate processors associated with the input port.
11. The packet-processing system of claim 10 , further comprising a plurality of instruction memories, each of the plurality of instruction memories being associated with a corresponding one of the plurality of candidate processors, wherein the plurality of instruction memories contain an identical instruction set.
12. The packet-processing system of claim 9 , wherein the at least one portion of the packet corresponds to a header of the packet.
13. The packet-processing system of claim 12 , wherein the ingress element comprises a state machine configured to write the packet header to a fixed location in the register file.
14. A method of processing a packet stream comprising a temporal sequence of packets, the method comprising the steps of:
providing a plurality of identical processors executing a common instruction set, each processor storing the instruction set locally to the processor;
receiving the packets;
for each packet, (i) identifying a packet header portion of the data packet by splitting the packet into a packet header portion and a packet body portion, (ii) selecting, by an ingress element, a processor from among the plurality to process the packet header based on processor availability, and (iii) causing the selected processor to process the packet header without invoking at least one of a load instruction and a store instruction; and assembling, by an egress element, the processed packets to reconstruct the packet stream in accordance with the temporal sequence.
15. The method of claim 14 wherein the plurality of processors is physically located on a plurality of integrated circuits.
16. A system for processing a packet stream comprising a temporal sequence of packets, the system comprising:
a plurality of identical processors executing a common instruction set, each processor comprising a local instruction memory containing the instruction set;
an input port for receiving the packets;
an ingress logic unit coupled to the input port and the processors, the ingress logic unit being configured, for each packet, to (i) identify a packet header portion of the data packet by splitting the packet into a packet header portion and a packet body portion and (ii) select a processor from among the plurality to process the packet header based on processor availability, the selected processor responding to the ingress logic unit by processing the packet header without invoking at least one of a load instruction and a store instruction; and
an egress logic unit for assembling the processed packets to reconstruct the packet stream in accordance with the temporal sequence.
17. The system of claim 16 wherein the plurality of processors is physically located on a plurality of integrated circuits.