Fabrication method for silicon-on defect layer in field-effect and bipolar transistor devices
View Patent ↗Semiconductor devices have device regions in which semiconductor properties such as spreading resistivity and its profile are significant. In making a p-type device region on a semiconductor wafer, an initial semiconductor device region is defined by a buried region, and an initial spreading resistivity profile is developed by annealing. After annealing, semiconductor device properties can be enhanced by removing a surface sub-region of the initial device region, and can be further improved by epitaxially growing thereon a monocrystalline film as an improved channel layer for FET devices. Such properties are relevant in MOS as well as bipolar devices.
1. A method for making a semiconductor device having a p-type device region, comprising the steps of:
(i) forming an initial region to an initial depth from at least a portion of an initial surface of a semiconductor substrate which has a conductivity type and an original bulk spreading resistivity,
(ii) heating said initial region, therein to develop an initial spreading resistivity profile having a peak, with peak value greater than said bulk spreading resistivity,
(iii) removing material from said initial surface portion, thereby forming said p-type device region having a new surface from which said resistivity peak is at a reduced depth, whereby said p-type device region has a final resistivity profile having a gradient which is significantly greater than gradient of said initial spreading resistivity profile.
2. The method of claim 1 , wherein step (i) comprises implanting particles.
3. The method of claim 2 , wherein said particles are selected from the group consisting of neutrons, protons, hydrogen ions, inert-gas ions and metallic ions.
4. The method of claim 1 , wherein said substrate has p-type conductivity.
5. The method of claim 1 , wherein said substrate has n-type conductivity and wherein, in step (ii), heating results in a change of conductivity to p type in said initial region.
6. The method of claim 5 , wherein heating for changing said conductivity type is distinct from heating to develop said initial spreading resistivity profile.
7. The method of claim 1 , wherein step (iii) comprises at least one of plasma etching, chemical etching and chemical-mechanical polishing.
8. The method of claim 1 , further comprising a step of selectively implanting dopant ions in said device region for forming channels for charge carriers.
9. The method of claim 1 , further comprising a step of selectively implanting dopant ions in said device region for forming source and drain regions.
10. The method of claim 1 , further comprising forming a CMOS structure in said p-type device region.
11. The method of claim 10 , wherein forming said CMOS structure comprises forming a trench between NMOS and PMOS devices, to a depth of at least to said depth of said peak of said spreading resistivity of said p-type device region.
12. The method of claim 1 , further comprising a step of epitaxially growing a crystalline region on said p-type device region.
13. The method of claim 1 , wherein heating of said initial region is to a temperature of approximately at least 900 degrees C.