Wireless device which uses an upper MAC and lower MAC interface
View Patent ↗The division of the 802.11 MAC operation into a lower MAC and an upper MAC is described. The lower MAC functionality is provided by a combination of software commands and an RF driver. The RF driver is intended to be appliance independent and will not change based on what type of 802.11 node is being implemented: Mobile Unit (MU), Access Point (AP), Wireless AP (WLAP), phone, pager, etc. The RF driver is not hardware platform independent, due to variations in DMA capability and allotted timers. The upper MAC is intended to be hardware platform independent, but appliance dependent (i.e. it will change based on the product being implemented such as PCMCIA, USB, PCI, etc.).
1. A system for processing radio frequency signals, comprising:
a transceiver for the reception and transmission of radio frequency signals;
a frequency converter for converting the radio frequency signals into an analog baseband signal, the analog baseband signal having a frequency less than the frequency of the radio frequency signal;
a baseband processor for converting the analog baseband signal into a corresponding digital signal;
a host device;
a first media access interface having a first media access architecture for processing the digital signal to provide information to the host device;
a second media access interface having a second media access architecture for processing the digital signal to provide information to the host device;
wherein the first media access architecture is primarily independent from the host device; and
wherein the second media access architecture is primarily dependent on the host device.
2. The system of claim 1 wherein the first media access interface and the frequency converter are housed on a first chipset; and
wherein the second media access interface is housed on a second chipset.
3. The system of claim 1 wherein the first media access interface, the frequency converter, and the transceiver are housed a first chipset; and
wherein the second media access interface is housed on a second chipset.
4. The system as in claim 2 , wherein the first media access architecture comprises a data store having host device data corresponding to the properties of host device.
5. The system as in claim 4 , wherein the host device data represents the bus size of the host device.
6. The system as in claim 5 , wherein the data store comprises a plurality of double synchronizing flip flops capable of operating asynchrously with the first media access interface.
7. The system as in claim 5 , wherein the data store is implemented using software.