IP Library Granted Patent US 6,998,595
Granted Patent B2
US 6,998,595 · App. 09/802,792 · Granted Feb 14, 2006

Color filter configuration for a silicon wafer to be diced into photosensitive chips

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Quick Facts
Patent No.
US 6,998,595
App. No.
09/802,792
Granted
Feb 14, 2006
Kind
B2
Abstract

An architecture and manufacturing method for photosensitive chips, such as used in office equipment and digital cameras, involves creating grooves between chip areas in a wafer, and then placing a light-transmissive planar layer over the main surface of the wafer. The planar layer, which may be acrylic-based, creates a substantially planar surface over both the photosites in the chip areas and the grooves. The planar layer in turn supports one or more light-transmissive filtering layers. The arrangement avoids damage to the filtering layers when the wafer is diced along the grooves.

Claims (13)

1. An imaging apparatus having a first photosensitive chip, the chip comprising:

a main surface, having at least one photosite thereon, the main surface defining an edge;

a groove portion defined at the edge;

a light-transmissive planar layer disposed over the main surface, the planar layer forming a planar surface substantially parallel with the main surface, the planar layer extending over the groove portion; and

a light-transmissive filtering layer disposed over the planar layer.

2. The apparatus of claim 1 , the planar layer comprising acrylic.

3. The apparatus of claim 1 , the filtering layer comprising acrylic.

4. The apparatus of claim 1 , the planar layer being substantially transmissive of visible light, and the filtering layer being transmissive of a predetermined range of wavelengths of light.

5. The apparatus of claim 1 , the filtering layer comprising a first portion transmissive of a first predetermined range of wavelengths of light and a second portion transmissive of a second predetermined range of wavelengths of light.

6. The apparatus of claim 5 , the chip including a plurality of photosites on the main surface thereof, the first portion being disposed over a first set of photosites on the first chip and the second portion being disposed over a second set of photosites on the first chip.

7. The apparatus of claim 1 , further comprising a second photosensitive chip, the second chip having a planar layer and a filtering layer arranged substantially similarly to the first chip.

8. The apparatus of claim 1 , further comprising a second photosensitive chip, the second chip having a plurality of photosites thereon, the first chip and the second chip being arranged to yield a single functional array of photosites.

9. The apparatus of claim 8 , the second chip having a planar layer and a filtering layer arranged substantially similarly to the first chip.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Sep 7, 2022
From: JPMORGAN CHASE BANK, N.A. AS SUCCESSOR-IN-INTEREST ADMINISTRATIVE AGENT AND COLLATERAL AGENT TO BANK ONE, N.A.
To: XEROX CORPORATION
Reel/Frame 061388/0388 →
RELEASE OF SECURITY INTEREST Recorded Sep 7, 2022
From: JPMORGAN CHASE BANK, N.A. AS SUCCESSOR-IN-INTEREST ADMINISTRATIVE AGENT AND COLLATERAL AGENT TO JPMORGAN CHASE BANK
To: XEROX CORPORATION
Reel/Frame 066728/0193 →